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MC74LCX373MELG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2013
June, 2017 − Rev. 14
1 Publication Order Number:
MC74LCX373/D
MC74LCX373
Low-Voltage CMOS
Octal Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The MC74LCX373 is a high performance, non−inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A V
I
specification of 5.5 V allows
MC74LCX373 inputs to be safely driven from 5 V devices.
The MC74LCX373 contains 8 D−type latches with 3−state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e.,
a latch output will change state each time its D input changes. When
LE is LOW, the latches store the information that was present on the D
inputs a setup time preceding the HIGH−to−LOW transition of LE.
The 3−state standard outputs are controlled by the Output Enable (OE
)
input. When OE
is LOW, the standard outputs are enabled. When OE
is HIGH, the standard outputs are in the high impedance state, but this
does not interfere with new data entering into the latches.
Features
• Designed for 2.3 to 3.6 V V
CC
Operation
• 5 V Tolerant − Interface Capability With 5 V TTL Logic
• Supports Live Insertion and Withdrawal
• I
OFF
Specification Guarantees High Impedance When V
CC
= 0 V
• LVTTL Compatible
• LVCMOS Compatible
• 24 mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in all Three Logic States (10 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500 mA
• ESD Performance:
♦ Human Body Model >2000 V
♦ Machine Model >200 V
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
1
20
MARKING
DIAGRAMS
LCX373 = Specific Device Code
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = Pb−Free Package
SOIC−20 WB
DW SUFFIX
CASE 751D
LCX373
AWLYYWWG
LCX
373
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
1
1
20
1
20
20
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
www.onsemi.com
(Note: Microdot may be in either location)
MC74LCX373
www.onsemi.com
2
Figure 1. Pinout (Top View)
PIN NAMES
FUNCTION
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
PINS
OE
LE
D0−D7
O0−O7
Figure 2. Logic Diagram
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
O7 D7 D6 O6 O5 D5 D4 O4 LE
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
OE
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
11
1
TRUTH TABLE
INPUTS OUTPUTS
OPERATING MODE
OE LE Dn On
L
L
H
H
H
L
H
L
Transparent (Latch Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled) Read Latch
L L X NC Hold; Read Latch
H L X Z Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level
h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
NC = No Change, State Prior to the Latch Enable High−to−Low Transition
X = High or Low Voltage Level or Transitions are Acceptable
Z = High Impedance State
For I
CC
Reasons DO NOT FLOAT Inputs
MC74LCX373
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Condition Units
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
I
DC Input Voltage −0.5 ≤ V
I
≤ +7.0 V
V
O
DC Output Voltage −0.5 ≤ V
O
≤ +7.0 Output in 3−State V
−0.5 ≤ V
O
≤ V
CC
+ 0.5 Output in HIGH or LOW State (Note 1) V
I
IK
DC Input Diode Current −50 V
I
< GND mA
I
OK
DC Output Diode Current −50 V
O
< GND mA
+50 V
O
> V
CC
mA
I
O
DC Output Source/Sink Current ±50 mA
I
CC
DC Supply Current Per Supply Pin ±100 mA
I
GND
DC Ground Current Per Ground Pin ±100 mA
T
STG
Storage Temperature Range −65 to +150 °C
MSL Moisture Sensitivity Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Units
V
CC
Supply Voltage
Operating
Data Retention Only
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
V
I
Input Voltage 0 5.5 V
V
O
Output Voltage
(HIGH or LOW State)
(3−State)
0
0
V
CC
5.5
V
I
OH
HIGH Level Output Current
V
CC
= 3.0 V − 3.6 V
V
CC
= 2.7 V − 3.0 V
V
CC
= 2.3 V − 2.7 V
−24
−12
−8
mA
I
OL
LOW Level Output Current
V
CC
= 3.0 V − 3.6 V
V
CC
= 2.7 V − 3.0 V
V
CC
= 2.3 V − 2.7 V
+24
+12
+8
mA
T
A
Operating Free−Air Temperature −40 +85 °C
Dt/DV
Input Transition Rise or Fall Rate, V
IN
from 0.8 V to 2.0 V, V
CC
= 3.0 V 0 10 ns/V
P1-P3P4-P6P7-P8

MC74LCX373MELG

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Buy MC74LCX373MELG
Manufacturer:
ON Semiconductor
Description:
IC LATCH TRANSP OCT LV 20-SOEIAJ
Lifecycle:
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