Description
The AFBR-56xxZ/AFCT-56xxZ family of interface convert-
ers meet the Gigabit Interface Converter specication
Rev. 5.4, an industry standard. The family provides a
uniform form factor for a wide variety of standard con-
nections to transmission media. The converters can be
inserted or removed from a host chassis without remov-
ing power from the host system.
The converters are suitable for interconnections in the
Gigabit Ethernet hubs and switches environment. The
design of these converters is also practical for other high
performance, point-to-point communication requiring
gigabit interconnections. Since the converters are hot-
pluggable, they allow system conguration changes
simply by plugging in a dierent type of converter.
The mechanical and electrical interfaces of these convert-
ers to the host system are identical for all implementa-
tions of the converter regardless of external media type.
A 20-pin connector is used to connect the converter to
the host system. Surge currents are eliminated by using
pin sequencing at this connector and a slow start circuit.
Two ground tabs at this connector also make contact
before any other pins, discharging possible component-
damaging static electricity. In addition, the connector it-
self performs a two-stage contact sequence. Operational
signals and power supply ground make contact in stage
1 while power makes contact in stage 2.
Applications
Switch to switch interface
High speed I/O for le servers
Bus extension applications
Features
RoHS Compliance
Compliant with Gigabit Interface Converter
specication Rev. 5.4 (1)
AFBR-5601Z is compliant with proposed
specications for IEEE 802.3z/D5.0 Gigabit Ethernet
(1000 Base-SX)
AFCT-5611Z is compliant with the ANSI 100-SM-LC-L
revision 2 10 km link specication
Performance:
AFBR-5601Z:
500 m with 50/125 µm MMF
220 m with 62.5/125 µm MMF
AFCT-5611Z:
550 m with 50/125 µm MMF
550 m with 62.5/125 µm MMF
10 km with 9/125 µm SMF
Horizontal or vertical installation
AEL Laser Class 1 eye safe per IEC 60825-1
AEL Laser Class I eye safe per US 21 CFR
Hot-pluggable
Related Products
850 nm VCSEL, 1 x 9 and SFF transceivers for 1000
base SX applications (HFBR-53D5, HFBR-5912E)
1300 nm, 1 x 9 Laser transceiver for 1000 base-LX
applications (HFCT-53D5)
Physical layer ICs available for optical interface
(HDMP-1636A/46A)
AFBR-5601Z and AFCT-5611Z
Gigabit Interface Converters (GBIC) for Gigabit Ethernet
Data Sheet
Patent - www.avagotech.com/patents
2
The AFBR-5601Z has been developed with 850 nm short
wavelength VCSEL technology while the AFCT-5611Z is
based on 1300 nm long wavelength Fabry Perot laser
technology.
The AFBR-5601Z complies with Annex G of the GBIC
specication Revision 5.4. In the 1000 BASE-SX environ-
ment the AFBR-5601Z achieves 220 m transmission
distance with 62.5 µm and 500 m with 50 µm multimode
ber respectively.
The AFCT-5611Z complies with Annex F of the GBIC
specication Revision 5.4 and reaches 10 km with 9/125
µm single mode ber. Both the AFBR-5601Z and the
AFCT-5611Z are Class 1 Eye Safe laser devices.
Serial Identication
The AFBR-56xxZ and AFCT-5611Z family complies with
Annex D (Module Denition 4) of the GBIC specica-
tion Revision 5.4, which denes the Serial Identication
Protocol.
Denition 4 species a serial denition protocol. For this
denition, upon power up, MOD_DEF(1:2) (Pins 5 and
6 on the 20-pin connector) appear as NC. Pin 4 is TTL
ground. When the host system detects this condition, it
activates the public domain serial protocol. The protocol
uses the 2-wire serial CMOS E
2
PROM protocol of the AT-
MEL AT24C01A or similar.
The data transfer protocol and the details of the manda-
tory and vendor specic data structures are dened in
Annex D of the GBIC specication Revision 5.4.
Regulatory Compliance
See the Regulatory Compliance Table for the targeted
typical and measured performance for these transceiv-
ers.
The overall equipment design will determine the level it
is able to be certied to. These transceiver performance
targets are oered as a gure of merit to assist the de-
signer in considering their use in equipment designs.
Note: AFBR-5601Z is non-compliant for Tx fault timing.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The rst case is during handling of the transceiver prior
to inserting it into the host system. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These precautions include using grounded wrist
straps, work benches, and oor mats in ESD controlled
areas.
The second case to consider is static discharges during
insertion of the GBIC into the host system. There are two
guide tabs integrated into the 20-pin connector on the
GBIC. These guide tabs are connected to circuit ground.
When the GBIC is inserted into the host system, these
tabs will engage before any of the connector pins. The
mating connector in the host system must have its tabs
connected to circuit ground. This discharges any stray
static charges and establishes a reference for the power
supplies that are sequenced later.
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high-speed trans-
ceivers from Avago Technologies will be required to meet
the requirements of FCC in the United States, CENELEC
EN55022 (CISPR 22) in Europe and VCCI in Japan.
Immunity
Equipment utilizing these transceivers will be subject to
radio-frequency electromagnetic elds in some environ-
ments. These transceivers have good immunity to such
elds due to their shielded design.
Eye Safety
Laser-based GBIC transceivers provide Class 1 (IEC 60825-
1) and Class I (US 21 CFR[J]) laser eye safety by design.
Avago Technologies has tested the current transceiver
design for compliance with the requirements listed below
under normal operating conditions and for compliance
under single fault conditions.
Outline Drawing
An outline drawing is shown in Figure 1. More detailed
drawings are shown in Gigabit Interface Converter speci-
cation Rev. 5.4.
3
Notes:
Blanks in ASCII column are numeric values not ASCII characters.
1. Address 63 and 95 are check sums. Address 63 is the check sum for bytes 0-62 and address 95 is the check sum for bytes 64-94.
Addr Hex ASCII Addr Hex ASCII Addr Hex ASCII Addr Hex ASCII
0 1 40 41 A 68 39 9 96 20
1 7 41 46 F 69 38 8 97 20
2 1 42 42 B 70 30 0 98 20
3 0 43 52 R 71 36 6 99 20
4 0 44 2D - 72 32 2 100 20
5 0 45 35 5 73 33 3 101 20
6 1 46 36 6 74 30 0 102 20
7 0 47 30 0 75 33 3 103 20
8 0 48 31 1 76 32 2 104 20
9 0 49 5A Z 77 38 8 105 20
10 0 50 20 78 33 3 106 20
11 1 51 20 79 34 4 107 20
12 0D 52 20 80 33 3 108 20
13 0 53 20 81 37 7 109 20
14 0 54 20 82 33 3 110 20
15 0 55 20 83 30 0 111 20
16 32 56 30 0 84 39 9 112 20
17 16 57 30 0 85 38 8 113 20
18 0 58 30 0 86 30 0 114 20
19 0 59 30 0 87 36 6 115 20
20 41 A 60 03 88 32 2 116 20
21 56 V 61 52 89 33 3 117 20
22 41 A 62 0 90 30 0 118 20
23 47 G 63 Note 1 91 30 0 119 20
24 4F O 64 0 92 0 120 20
25 20 65 1A 93 0 121 20
26 20 66 0 94 0 122 20
27 20 67 0 95 Note1 123 20
28 20 124 20
29 20 125 20
30 20 126 20
31 20 127 20
32 20
33 20
34 20
35 20
36 0
37 00
38 17
39 6A
GBIC Serial ID Memory Contents - AFBR-5601Z

AFBR-5601Z

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
Fiber Optic Transmitters, Receivers, Transceivers GbE SX GBIC TXCBR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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