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ZL2004ALNN-01

P1-P3P4-P6P7-P7
1
Adaptive Digital DC/DC Controller with Current Sharing
ZL2004-01
The ZL2004-01 is specialized version of the ZL2004 DC/DC
controller that has been optimized for high output accuracy
within a given set of operating conditions. The ZL2004-01 is
otherwise identical to the ZL2004 in features and functionality.
The ZL2004-01 has been optimized for use with the ZL1505
MOSFET driver and discrete MOSFETs.
The ZL2004-01 integrates a proprietary Digital-DC
communication bus for current sharing and inter device
communication. Adaptive algorithms improve light load
efficiency. All operating features can be configured by simple pin-
strap selection, resistor selection or through the on-board serial
port. The PMBus™-compliant ZL2004-01 uses the SMBus™ serial
interface for communication with other Digital-DC products or a
host controller.
Related Literature
•See FN6846, ZL2004 “Adaptive Digital DC-DC Controller with
Current Sharing”
Features
•Power Conversion
• Efficient synchronous buck controller
• ± 0.2% VOUT set-point accuracy
• 8.0V to 10.0V input range
•0.9V to 1.1V output range
• Adaptive performance optimization algorithms
• Fast load transient response
• Active current sharing
• DCR current sensing with digitally adjustable current sense range
• RoHS compliant (5mmx5mm) QFN package
• Power Management
• Digital soft-start/stop
• Precision delay and ramp-up
• Power-good/enable
• Voltage tracking, sequencing and margining
• Voltage/current/temperature monitoring
• SMBus communication (PMBus compliant)
• Output voltage and current protection
• Internal non-volatile memory (NVM)
Applications
• Servers/storage equipment
• Telecom/datacom equipment
• Power supplies (memory, DSP, ASIC, FPGA)
CURRENT
SENSE
LDO
TEMP
SENSOR
V (0,1)
VMON
MGN
VR VDD
PWML
ISENA
ISENB
POWER
LEVEL
SHIFTER
XTEMP
PWM
I
2
C
SCL
SDA
SALRT
SA (0,1)
MANAGEMENT
EN
PG CFG FLEXSS ILIMFC
MONITOR
CONTROLLER
V25
SYNC
SGND DGND
ADC
NON-
VOLATILE
MEMORY
VTRK
VSEN+/-
DDC
PWMH
FIGURE 1. BLOCK DIAGRAM
May 23, 2011
FN6847.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas Inc. 2009-2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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8
1
0
1
a
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Z
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6
1
0
5
ZL2004-01
2
FN6847.2
May 23, 2011
Pin Configuration
ZL2004-01
(32 LD QFN)
TOP VIEW
Ordering Information
PART NUMBER
(Notes 1, 4)
PART
MARKING
TEMP RANGE
(°C) SHIPPING CONTAINER
PACKAGE
Tape & Reel
(Pb-free) PKG. DWG. #
ZL2004ALNN-01 (Note 2) 2004-01 0 to +65 490 pieces 32 Ld QFN L32.5x5D
ZL2004ALNNT-01 (Note 2) 2004-01 0 to +65 100 pieces 32 Ld QFN L32.5x5D
ZL2004ALNNT1-01 (Note 2) 2004-01 0 to +65 1000 pieces 32 Ld QFN L32.5x5D
ZL2004ALNF-01 (Note 3) 2004-01 0 to +65 490 pieces 32 Ld QFN L32.5x5G
ZL2004ALNFT-01 (Note 3) 2004-01 0 to +65 100 pieces 32 Ld QFN L32.5x5G
ZL2004ALNFT1-01 (Note 3) 2004-01 0 to +65 1000 pieces 32 Ld QFN L32.5x5G
NOTES:
1. Please refer to TB347
for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate -
e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ZL2004-01
. For more information on MSL please see techbrief TB363.
PG
SS
EN
CFG
MGN
DDC
XTEMP
V25
FC
V0
V1
VIMON
NC
VRTK
VSEN+
VSEN-
DGND
SYNC
SA0
SA1
ILIM
SCL
SDA
SALRT
VDD
VR
PWMH
SGND
PWML
ISENA
ISENB
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
9 10111213141516
EXPOSED PADDLE
CONNECT TO SGND
ZL2004-01
3
FN6847.2
May 23, 2011
Pin Descriptions
PIN SYMBOL
TYPE
(Note 5) DESCRIPTION
1 DGND PWR Digital ground. Connect to low impedance ground plane.
2SYNCI/O, M
(Note 6)
Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external
clock or to output internal clock.
3 SA0 I, M Serial address select pins. Used to assign unique address for each individual device or to enable certain
management features.
4SA1
5 ILIM I, M Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
6 SCL I/O Serial clock. Connect to external host and/or to other ZL devices.
7 SDA I/O Serial data. Connect to external host and/or to other ZL devices.
8 SALRT O Serial alert. Connect to external host if desired.
9 FC I Loop compensation selection pin.
10 V0 I, M Output voltage selection pins. Used to set V
OUT
set-point and V
OUT
max.
11 V1
12 VMON I, M External voltage monitoring (Can be used for external driver bias monitoring for Power-good).
13, 17 NC No Connect.
14 VTRK I Tracking sense input. Used to track an external voltage source.
15 VSEN+ I Differential Output voltage sense feedback. Connect to positive output regulation point.
16 VSEN- I Differential Output voltage sense feedback. Connect to negative output regulation point.
18 ISENB I Differential voltage input for current sensing.
19 ISENA I Differential voltage input for current sensing. High voltage (DCR).
20 PWML O PWM Gate low signal.
21 SGND PWR Connect to low impedance ground plane. Internal connection to SGND.
22 PWMH O PWM Gate High signal.
23 VR PWR Internal 5V reference used to power internal drivers.
24 VDD
(Note 7)
PWR Supply voltage.
25 V25 PWR Internal 2.5V reference used to power internal circuitry.
26 XTEMP I External temperature sensor input. Connect to external 2N3904 (Base Emitter junction).
27 DDC I Single wire DDC bus (Current sharing, interdevice communication).
28 MGN I V
OUT
margin control.
29 CFG M Configuration pin. Used to control the switching phase offset, sequencing and other management features.
30 EN I Enable. Active signal enables PWM switching.
31 SS I, M Soft-start delay and ramp select. Sets the delay from when EN is asserted until the output voltage starts to
ramp and the ramp time.
32 PG O Power-good output.
EPAD SGND PWR Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
NOTES:
5. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
6. The SYNC pin can be used as a logic pin, a clock input or a clock output.
7. V
DD
is measured internally and the value is used to modify the PWM loop gain.
P1-P3P4-P6P7-P7

ZL2004ALNN-01

Mfr. #:
Buy ZL2004ALNN-01
Manufacturer:
Renesas / Intersil
Description:
IC REG CTRLR BUCK PMBUS 32QFN
Lifecycle:
New from this manufacturer.
Delivery:
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