DC1564A-D Datasheet DC1564A-D, DC1564A-C, DC1564A-E | P1-P3

dc1564afa

DEMO MANUAL DC1564A

the DC1564 is supplied with the appropriate ADC. The

circuitry on the analog inputs is optimized for analog input

frequencies from 5MHz to 140MHz. Refer to the data sheet

for proper input networks for different input frequencies.

Design files for this circuit board are available at

http://www.linear.com/demo

Description

LTC2158-14, LTC2158-12,

LTC2157-14, LTC2157-12,

LTC2156-14, LTC2156-12,

LTC2155-14, LTC2155-12

12-Bit/14-Bit, 170Msps to

310Msps Dual ADCs

Demonstration circuit 1564A supports a family of

12-/14-bit 170Msps to 310Msps ADCs. Each assembly

features one of the following devices: LTC

2158-14/

LTC2158-12, LTC2157-14/LTC2157-12, LTC2156-14/

LTC2156-12, LTC2155-14/LTC2155-12, high speed, dual

ADCs.

The versions of the 1564A demo board are listed in Table1.

Depending on the required resolution and sample rate,

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope

is a trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners.

performance summary

= 25°C)

Table 1. DC1564A Variants

DC1564A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY

1564A-A LTC2157-14 14-Bit 250Msps 5MHz to 140MHz

1564A-B LTC2156-14 14-Bit 210Msps 5MHz to 140MHz

1564A-C LTC2155-14 14-Bit 170Msps 5MHz to 140MHz

1564A-D LTC2157-12 12-Bit 250Msps 5MHz to 140MHz

1564A-E LTC2156-12 12-Bit 210Msps 5MHz to 140MHz

1564A-F LTC2155-12 12-Bit 170Msps 5MHz to 140MHz

1564A-G LTC2158-14 14-Bit 310Msps 5MHz to 140MHz

1564A-H LTC2158-12 12-Bit 310Msps 5MHz to 140MHz

PARAMETER CONDITION VALUE

Supply Voltage – DC1564A Depending on Sampling Rate and the A/D Converter

Provided, This Supply Must Provide Up to 500mA.

Optimized for 3.6V [3V ⇔ 6.0V Min/Max]

Analog input range Depending on SENSE Pin Voltage 1.5V

P-P

or 1.32V

P-P

Logic Input Voltages Minimum Logic High 1.3V

Maximum Logic Low 0.6V

Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) 350mV/1.25V Common Mode

Minimum Logic Levels (100Ω Load, 3.5mA Mode) 247mV/1.25V Common Mode

Sampling Frequency (Convert Clock Frequency) See Table 1

Encode Clock Level Differential Encode Mode (ENC

–

Not Tied to GND) 0.2V to 1.9V

Resolution See Table 1

dc1564afa

DEMO MANUAL DC1564A

Figure 1. DC1564A Setup (Zoom for Detail)

Demonstration circuit 1564A is easy to set up to evaluate

the performance of the LTC2157 A/D converter family. Refer

to Figure 1 for proper measurement equipment setup and

follow the procedure below:

Setup

If a DC1371 Data Acquisition and Collection System was

supplied with the DC1564A demonstration circuit, fol-

low the DC1371 Quick Start Guide to install the required

software and for connecting the DC1371 to the DC1564A

and to a PC.

CHANNEL 2

SINGLE-ENDED ENCODE CLOCK

(USE A LOW JITTER SIGNAL GENERATOR

WITH PROPER FILTERING)

CHANNEL 1

ANALOG INPUTS

PARALLEL/SERIAL

3.6V TO 6V

TO PROVIDED

POWER SUPPLY

TO PROVIDED

USB CABLE

DC1564A Demonstration Circuit Board Jumpers

The DC1564A demonstration circuit board should have

the following jumper settings as default positions: (as

per Figure 1)

JP1 – PAR/SER: Selects Parallel or Serial Programming

Mode. (Default: Serial)

Applying Power and Signals to the DC1564A

Demonstration Circuit

The DC1371 is used to acquire data from the DC1564A,

the DC1371 must first be connected to a powered USB

port and have 5V applied power before applying 3.6V to

performance summary

= 25°C)

Quick start proceDure

Input Frequency Range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

dc1564afa

DEMO MANUAL DC1564A

Quick start proceDure

6.0V across the pins marked V+ and GND on the DC1564A.

The DC1564 requires 3.6V for proper operation.

Regulators on the board produce the voltages required for

the ADC. The DC1564A demonstration circuit requires up

to 500mA depending on the sampling rate and the A/D

converter supplied.

The DC1564A should not be removed, or connected to

the DC1371 while power is applied.

Analog Input Network

For optimal distortion and noise performance the RC

network on the analog inputs may need to be optimized

for different analog input frequencies. For input freq-

uencies above 140MHz, refer to the respective ADC data

sheet for a proper input network. Other input net-

works may be more appropriate for input frequencies

less that 5MHz.

In almost all cases, filters will be required on both analog

input and encode clock to provide data sheet SNR.

The filters should be located close to the inputs to avoid

reflections from impedance discontinuities at the driven

end of a long transmission line. Most filters do not present

50Ω outside the passband. In some cases, 3dB to 10dB

pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without

distortion, you may benefit from a medium power amplifier

based on a Gallium Arsenide Gain block prior to the final

filter. This is particularly true at higher frequencies where

IC-based operational amplifiers may be unable to deliver

the combination of low noise figure and high IP3 point

required. A high order filter can be used prior to this final

amplifier, and a relatively lower Q filter used between the

amplifier and the demo circuit.

Apply the analog input signal of interest to the SMA con-

nectors on the DC1564A demonstration circuit board

marked J2 AINA and J3 AINB. These inputs correspond

with channels one and two of the ADC respectively. These

inputs are capacitively coupled to Balun transformers

ETC1-1-13 (lead free part number: MABA007159-000000).

Encode Clock

Note: Apply an encode clock to the SMA connector on

the DC1564A demonstration circuit board marked J4

CLK+. As a default the DC1564A is populated to have a

single-ended input.

For the best noise performance, the encode input must

be driven with a very low jitter, sine wave source. The

amplitude should be large, up to 3V

P-P

or 13dBm.

Using bandpass filters on the clock and the analog input will

improve the noise performance by reducing the wideband

noise power of the signals. Data sheet FFT plots are taken

with 10-pole LC filters made by TTE (Los Angeles, CA) to

suppress signal generator harmonics, non-harmonically

related spurs and broadband noise. Low phase noise

Agilent 8644B generators are used for both the clock input

and the analog input.

Digital Outputs

The data outputs, data clock, and frame clock signals are

available on J1 of the DC1564A. This connector follows the

VITA-57/FMC standard, but all signals should be verified

when using an FMC carrier card other than the DC1371.

Software

The DC1371 is controlled by the PScope™ system soft-

ware provided or downloaded from the Linear Technology

website at http://www.linear.com/software/.

To start the data collection software, if PScope.exe is in-

stalled (by default) in \Program Files\LTC\PScope\, double

click the PScope icon or bring up the run window under

the start menu and browse to the PScope directory and

select PScope.

If the DC1564A demonstration circuit is properly connected

to the DC1371, PScope should automatically detect the

DC1564A, and configure itself accordingly.

If everything is hooked up properly, powered, and a suitable

convert clock is present, clicking the Collect button will

result in time and frequency plots displayed in the PScope

window. Additional information and help for PScope is

available in the DC1371 Quick Start Guide and in the online

help available within the PScope program itself.

P1-P3 P4-P6 P7-P9 P10-P10

DC1564A-D

Mfr. #:

Buy DC1564A-D

Manufacturer:

Analog Devices Inc.

Description:

Data Conversion IC Development Tools LTC2157-12: 12-bit, 250Msps, 1.8V Dual A

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

DC1564A-D

DC1564A-D

Products related to this Datasheet