© Semiconductor Components Industries, LLC, 2017
February, 2017 − Rev. 5
1 Publication Order Number:
AX−SFEU/D
AX-SFEU, AX-SFEU-API
Ultra-Low Power,
AT Command / API Controlled,
Sigfox
)
Compliant
Transceiver IC for Up-Link
and Down-Link
OVERVIEW
Circuit Description
AX−SFEU and AX−SFEU−API are ultra−low power
single chip solutions for a node on the Sigfox network with
both up− and down−link functionality. The AX−SFEU chip
is delivered fully ready for operation and contains all the
necessary firmware to transmit and receive data from the
Sigfox network in Europe. It connects to the customer
product using a logic level RS232 UART. AT commands are
used to send frames and configure radio parameters.
The AX−SFEU−API variant is intended for customers
wishing to write their own application software based on the
AX−SF−LIB−1−GEVK library.
Features
Functionality and Ecosystem
Sigfox up−link and down−link functionality controlled
by AT commands or API
The AX−SFEU and AX−SF−API ICs are part of a
whole development and product ecosystem available
from ON Semiconductor for any Sigfox requirement.
Other parts of the ecosystem include
Ready to go development kit
DVK−SFEU−[API]−1−GEVK including a 2 year
Sigfox subscription
Sigfox Ready
®
certified reference design for the
AX−SFEU and AX−SFEU−API ICs
AX−SF10−MINI21−868−B1 and
AX−SF10−ANT21−868−B1, Sigfox compliant SMT
modules based on AX−SFEU with 50 W pads or chip
antenna. Not available for AX−SFEU−API
General Features
QFN40 5 mm x 7 mm package
Supply range 1.8 V* − 3.6 V
−40°C to 85°C
Temperature sensor
Supply voltage measurements
*The device is operational from 1.8 V to 3.6 V. However, a supply
voltage below 2.0 V is considered an extreme condition.
Details see Table 4.
10 GPIO pins
4 GPIO pins with selectable voltage measure
functionality, differential (1 V or 10 V range) or
single ended (1 V range) with 10 bit resolution
2 GPIO pins with selectable sigma delta DAC
output functionality
2 GPIO pins with selectable output clock
3 GPIO pins selectable as SPI master interface
Integrated RX/TX switching with differential
antenna pins
Power Consumption
Ultra−low Power Consumption:
Charge required to send a Sigfox OOB packet at
14 dBm output power: 0.28 C
Deepsleep mode current: 100 nA
Sleep mode current: 1.3 mA
Standby mode current: 0.5 mA
Continuous radio RX−mode at 869.525 MHz :
10 mA
Continuous radio TX−mode at 868.130 MHz
19 mA @ 0 dBm
49 mA @ 14 dBm
High Performance Narrow−band Sigfox RF Transceiver
Receiver
Carrier frequency 869.525 MHz
Data−rate 600 bps FSK
Sensitivity
−126 dBm @ 600 bps, 869.525 MHz, GFSK
0 dBm maximum input power
Transmitter
Carrier frequency 868.13 MHz
Data−rate 100 bps PSK
High efficiency, high linearity integrated power
amplifier
Maximum output power 14 dBm
Power level programmable in 1 dBm steps
Applications
Sigfox networks up−link and down−link.
www.onsemi.com
AX−SFEU, AX−SFEU−API
www.onsemi.com
2
BLOCK DIAGRAM
Figure 1. Functional Block Diagram of the AX−SFEU / AX−SFEU−API
RX/TX
switch and
antenna
interface
Transmit
Communication
controller
CPU
Program
memory
(FLASH)
Sigfox identity (ID, PAC)
Sigfox compliant
RAMpower mode control
ADC
GPIO
UART
RF synthesis
DAC
AX−SFEU / AX−SFEU−API
TCXO
interface
Receive
CLKP
CLKN
ANTP
ANTN
UARTRX
UARTTX
GPIO[9:0]
VDD_IO
VDD_ANA
GND
dedicated
status
outputs
RADIO_LED
CPU_LED
TX_LED
RX_LED
VTCXO
RESET_N
CAL
FILT
application
(AX−SFEU only)
AX−SFEU, AX−SFEU−API
www.onsemi.com
3
Table 1. PIN FUNCTION DESCRIPTIONS
Symbol Pin(s) Type Description
VDD_ANA 1 P Analog power output, decouple to neighboring GND
GND 2 P Ground, decouple to neighboring VDD_ANA
ANTP 3 A Differential antenna input/output
ANTN 4 A Differential antenna input/output
NC 5 N Do not connect
GND 6 P Ground, decouple to neighboring VDD_ANA
VDD_ANA 7 P Analog power output, decouple to neighboring GND
GND 8 P Ground
FILT 9 A Synthesizer filter
L2 10 A Must be connected to pin L1
L1 11 A Must be connected to pin L2
NC 12 N Do not connect
GPIO8 13 I/O/PU General purpose IO
GPIO7 14 I/O/PU General purpose IO, selectable SPI functionality (MISO)
GPIO6 15 I/O/PU General purpose IO, selectable SPI functionality (MOSI)
GPIO5 16 I/O/PU General purpose IO, selectable SPI functionality (SCK)
GPIO4 17 I/O/PU
General purpose IO, selectable SD DAC functionality, selectable dock
functionality
CPU_LED 18 O CPU activity indicator
RADIO_LED 19 O Radio activity indicator
VTCXO 20 O TCXO power
GPIO9 21 I/O/PU General purpose IO, wakeup from deep sleep
UARTTX 22 O UART transmit
UARTRX 23 I/PU UART receive
RX_LED 24 O Receive activity indicator
TX_LED 25 O Transmit activity indicator
NC 26 PD Do not connect
RESET_N 27 I/PU Optional reset pin. Internal pull−up resistor is permanently enabled,
nevertheless it is recommended to connect this pin to VDD_IO if it is not used.
GND 28 P Ground
VDD_IO 29 P Unregulated power supply
GPIO0 30 I/O/A/PU
General purpose IO, selectable ADC functionality, selectable SD DAC
functionality, selectable clock functionality
GPIO1 31 I/O/A/PU General purpose IO, selectable ADC functionality
GPIO2 32 I/O/A/PU General purpose IO, selectable ADC functionality
NC 33 N Do not connect
NC 34 N Do not connect
GPIO3 35 I/O/A/PU General purpose IO, selectable ADC functionality
VDD_IO 36 P Unregulated power supply
CAL 37 A Connect to FILT as shown in the application diagram
NC 38 N Connect to Ground
CLKN 39 A TCXO interface

AX-SFEU-1-01-TB05

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
RF System on a Chip - SoC SigFox SoC for Uplink/Downlink
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet