MAX3841ETG+

MAX3841
12.5Gbps CML 2
×
2 Crosspoint Switch
4 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 12 V
CC
+3.3V Core Supply Voltage
2, 5 VCC1IN Supply Voltage for CML Input IN1. Connect to 1.8V, 2.5V, or 3.3V.
3 IN1+ Positive Serial Data Input 1, CML
4 IN1- Negative Serial Data Input 1, CML
6 SEL1 Output 1 Select, LVCMOS Input. See Table 1.
7 SEL2 Output 2 Select, LVCMOS Input. See Table 1.
8, 11 VCC2IN Supply Voltage for CML Input IN2. Connect to 1.8V, 2.5V, or 3.3V.
9 IN2+ Positive Serial Data Input 2, CML
10 IN2- Negative Serial Data Input 2, CML
13, 24 GND Supply Ground
14, 17 VCC1OUT Supply Voltage for CML Output OUT1. Connect to 1.8V, 2.5V, or 3.3V.
15 OUT1- Negative Serial Data Output 1, CML
16 OUT1+ Positive Serial Data Output 1, CML
18 ENO1 Output 1 Enable, LVCMOS Input. See Table 1.
19 ENO2 Output 2 Enable, LVCMOS Input. See Table 1.
20, 23 VCC2OUT Supply Voltage for CML Output OUT2. Connect to 1.8V, 2.5V, or 3.3V.
21 OUT2- Negative Serial Data Output 2, CML
22 OUT2+ Positive Serial Data Output 2, CML
— EP
Exposed Pad. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
Detailed Description
The MAX3841 contains a pair of CML inputs that drive
two 2:1 multiplexers, with separate select inputs SEL1
and SEL2, providing a 2 × 2 crosspoint data path. The
outputs of the multiplexers each drive a high-perfor-
mance CML output that can be disabled (powered
down) using the ENO1/ENO2 inputs. All of the data
paths are fully differential to minimize jitter, crosstalk,
and signal skew. See Figure 1 for the functional diagram.
CML Input and Output Buffers
The MAX3841 input and output buffers are terminated
with 50Ω to independent supply lines, and are also com-
patible with 100Ω differential terminations. (See Figures 3
and 4.) Separate power-supply connections are provided
for the core, input buffers, and output buffers to allow DC-
coupling to 1.8V, 2.5V, or 3.3V CML ICs. If desired, the
CML inputs and outputs can be AC-coupled.
The CML inputs accept serial NRZ data with differential
amplitude from 150mV
P-P
to 1200mV
P-P
(see Figure 2).
The CML outputs provide 500mV
P-P
nominal differential
swing, resulting in low power consumption.
MAX3841
CML
CML
CML
CML
1
0
1
0
OUT1
ENO1
SEL1
OUT2
ENO2
SEL2
IN1
IN2
2
2
2
2
Figure 1. Functional Diagram
Applications Information
Select and Enable Controls
The MAX3841 provides two LVCMOS-compatible
select inputs, SEL1 and SEL2. Either data input can be
connected to either or both data outputs. The MAX3841
provides two LVCMOS-compatible enable inputs,
ENO1 and ENO2, so each output can be disabled
independently. The MAX3841 can also be used as a
1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using
the LVCMOS control inputs accordingly (see Table 1).
Power-Supply Connections
Each of the input and output power-supply connections
(VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is indepen-
dent and need not be connected to the same voltage.
The input and output supplies can be connected to
1.8V, 2.5V, or 3.3V, but the core supply (V
CC
) must be
connected to 3.3V for proper operation.
Input and Output Interfaces
The MAX3841 inputs and outputs can be AC-coupled
or DC-coupled according to the application. If an input
or output is not used it should be terminated with 50Ω
to the correct input or output supply voltage. For more
information about interfacing with logic families, refer to
Application Note 291:
HFAN-01.0: Introduction to
LVDS, PECL, and CML
.
Package and Layout Considerations
The MAX3841 is packaged in a 4mm × 4mm 24-pin thin
QFN with exposed pad. The exposed pad provides
thermal and electrical connectivity to the IC and must
be soldered to a high-frequency ground plane. Use
multiple vias to connect the exposed pad underneath
the package to the PC board ground plane.
Use good layout techniques for the 10Gbps PC board
transmission lines, and configure the layout near the IC to
minimize impedance discontinuities. Power-supply
decoupling capacitors should be located as close as
possible to the IC.
MAX3841
12.5Gbps CML 2
×
2 Crosspoint Switch
_______________________________________________________________________________________ 5
V-
V+
(V+) - (V-)
1200mV
MAX
600mV
MAX
75mV
MIN
150mV
MIN
Figure 2. Definition of Differential Voltage Swing
MAX3841
50Ω50Ω
VCC_IN
IN_+
IN_-
MAX3841
50Ω 50Ω
VCC_OUT
OUT_+
OUT_-
Figure 3. Equivalent CML Input Circuit
Figure 4. Equivalent CML Output Circuit
Table 1. Output Controls
ENO1 ENO2 SEL1 SEL2 OUT1 OUT2
0 0 0 0 IN2 IN1
0 0 0 1 IN2 IN2
0 0 1 0 IN1 IN1
0 0 1 1 IN1 IN2
1 1 X X Disabled Disabled
MAX3841
12.5Gbps CML 2
×
2 Crosspoint Switch
6 _______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 950
PROCESS: SiGe BiCMOS
1
V
CC
2
VCC1IN
3
IN1+
4
IN1-
5
VCC1IN
6
SEL1
7
SEL2
8
VCC2IN
9
IN2+
10
IN2-
11
VCC2IN
12
V
CC
13
GND
14
VCC1OUT
15
OUT1-
16
OUT1+
17
VCC1OUT
18
ENO1
19
ENO2
20
VCC2OUT
21
OUT2-
22
OUT2+
23
VCC2OUT
24
GND
MAX3841
THIN QFN
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE
SOLDERED TO GROUND FOR PROPER THERMAL AND
ELECTRICAL OPERATION.
TOP VIEW
*EP
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages
.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
24 TQFN-EP T2444-3
21-0139

MAX3841ETG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog & Digital Crosspoint ICs 12.5Gbps CML 2x2 Crosspoint Switch
Lifecycle:
New from this manufacturer.
Delivery:
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