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DSQ2102A-QA-00 June 2017www.richtek.com
RTQ2102A-QA
©
Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
The output ripple is highest at maximum input voltage
since ΔI
L
increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR, but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density, but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR, but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long term reliability. Ceramic capacitors
have excellent low ESR characteristics, but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Table 2. Capacitors for C
IN
and C
OUT
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T
J(MAX)
, listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction-to-ambient
thermal resistance.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θ
JA
, is highly package dependent. For a
WDFN-8L 3x3 package, the thermal resistance, θ
JA
, is
31°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at T
A
= 25°C can be calculated as below :
P
D(MAX)
= (125°C − 25°C) / (31°C/W) = 3.22W for a
WDFN-8L 3x3 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed T
J(MAX)
and the thermal
resistance, θ
JA
. The derating curves in Figure 2 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 2. Derating Curve of Maximum Power Dissipation
Component
Supplier
Part No.
Capacitance
(F)
Case
Size
MuRata GRM31CR71A106KA01 10F 1206
MuRata GRM31CR71A226KA01 22F 1206
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W) 1
Four-Layer PCB
