MC74VHCT540AMG

© Semiconductor Components Industries, LLC, 2011
June, 2011 Rev. 6
1 Publication Order Number:
MC74VHCT540A/D
MC74VHCT540A
Octal Bus Buffer
Inverting
The MC74VHCT540A is an advanced high speed CMOS inverting
octal bus buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The MC74VHCT540A features inputs and outputs on opposite
sides of the package and two ANDed activelow output enables.
When either OE1
or OE2 are high, the terminal outputs are in the
high impedance state.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT540A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply voltage
input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: t
PD
= 3.7 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 4.0 μA (Max) at T
A
= 25°C
TTLCompatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: V
OLP
= 1.2 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 124 FETs or 31 Equivalent Gates
These Devices are PbFree and are RoHS Compliant
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = PbFree Package
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MARKING
DIAGRAM
74VHCT540
AWLYWWG
SOEIAJ20
M SUFFIX
CASE 967
1
20
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1 OE2 A
H
L
Z
Z
Device Package Shipping
ORDERING INFORMATION
MC74VHCT540AMG SOEIAJ 40 Units/Rail
MC74VHCT540AMELG SOEIAJ 2000 Units/T&R
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
MC74VHCT540A
http://onsemi.com
2
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
OUTPUT
ENABLES
DATA
INPUTS
INVERTING
OUTPUTS
Figure 1. Logic Diagram Figure 2. Pin Assignment
A5
A3
A2
A1
OE1
GND
A8
A7
A6
A4 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Y3
Y2
Y1
OE2
V
CC
Y8
Y7
Y6
Y5
Y4
MC74VHCT540A
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3
MAXIMUM RATINGS (Note 1)
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current 20 mA
I
OK
Output Diode Current ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 75 mA
P
D
Power Dissipation in Still Air (Note 2)
SOIC Packages
TSSOP Package
500
450
mW
T
stg
Storage Temperature – 65 to + 150 _C
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximumrated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Derating SOIC Packages: – 7.0 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 4.5 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage Outputs in 3State
High or Low State
0
0
5.5
V
CC
V
T
A
Operating Temperature 55 125 _C
t
r
, t
f
Input Rise and Fall Time V
CC
= 5.0 V ±0.5 V 0 20 ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
(V)
T
A
= 25°C T
A
85°C T
A
125°C
Unit
Min Typ Max Min Max Min Max
V
IH
Minimum HighLevel Input
Voltage
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
V
IL
Maximum LowLevel Input
Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
OH
Minimum HighLevel Output
Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OH
= 50 μA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
IN
= V
IH
or V
IL
I
OH
= 4.0 mA
I
OH
= 8.0 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum LowLevel Output
Voltage
V
IN
= V
IH
or V
IL
V
IN
= V
IH
or V
IL
I
OL
= 50 μA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
IN
= V
IH
or V
IL
I
OL
= 4.0 mA
I
OL
= 8.0 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
IN
Maximum Input Leakage
Current
V
in
= 5.5 V or
GND
0 to 5.5 ±0.1 ±1.0 ±1.0 μA
I
CC
Maximum Quiescent Supply
Current
V
in
= V
CC
or GND 5.5 2.0 20 40 μA
I
CCT
Quiescent Supply Current Input: V
IN
= 3.4 V 5.5 1.35 1.50 1.65 mA
I
OPD
Output Leakage Current V
OUT
= 5.5 V 0.0 0.5 5.0 10 μA

MC74VHCT540AMG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Buffers & Line Drivers LOG CMOS BUFR 3ST OCTL
Lifecycle:
New from this manufacturer.
Delivery:
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