RT9741
10
DS9741-01 March 2015www.richtek.com
©
Copyright 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Layout Consideration
In order to meet the voltage drop, droop, and EMI
requirements, careful PCB layout is necessary. The
following guidelines must be followed :
Locate the ceramic bypass capacitors as close as
possible to the V
IN
pins of the RT9741.
Place a ground plane under all circuitry to lower both
resistance and inductance and improve DC and transient
performance (Use a separate ground and power plans if
possible).
Keep all V
BUS
traces as short as possible and use at
least 50-mil, 2 ounce copper for all V
BUS
traces.
Avoid via as much as possible. If via are necessary,
make them as large as feasible.
Place cuts in the ground plane between ports to help
reduce the coupling of transients between ports.
Locate the output capacitor and ferrite beads as close
to the USB connectors as possible to lower impedance
(mainly inductance) between the port and the capacitor
and improve transient load performance.
Locate the RT9741 as close as possible to the output
port to limit switching noise.
The input capacitor should be
placed as close as possible to
the IC.
GND
VIN VOUT
+
+
GND_BUS
V
BUS
+
Figure 3. PCB Layout Guide
