74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 10 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation delay CP to Qn; see Figure 8
[2]
V
CC
= 1.2 V - 17 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 7.1 13.1 1.5 15.1 ns
V
CC
= 2.3 V to 2.7 V 2.4 4.1 7.4 2.4 8.6 ns
V
CC
= 2.7 V 1.5 3.9 7.2 1.5 9.0 ns
V
CC
= 3.0 V to 3.6 V 1.5 3.7 6.6 1.5 10.0 ns
CP to TC
; see Figure 8
[2]
V
CC
= 1.2 V - 21 - - - ns
V
CC
= 1.65 V to 1.95 V 2.0 8.5 14.9 2.0 17.2 ns
V
CC
= 2.3 V to 2.7 V 3.0 4.9 8.4 3.0 9.7 ns
V
CC
= 2.7 V 1.5 4.7 8.8 1.5 11.0 ns
V
CC
= 3.0 V to 3.6 V 1.5 4.4 7.5 1.5 9.5 ns
CET
to TC; see Figure 9
[2]
V
CC
= 1.2 V - 19 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 6.6 12.3 1.5 14.2 ns
V
CC
= 2.3 V to 2.7 V 2.2 3.8 7.0 2.2 8.1 ns
V
CC
= 2.7 V 1.5 4.0 7.2 1.5 9.0 ns
V
CC
= 3.0 V to 3.6 V 1.5 3.4 6.2 1.5 8.0 ns
U/D
to TC; see Figure 10
[2]
V
CC
= 1.2 V - 21 - - - ns
V
CC
= 1.65 V to 1.95 V 1.0 7.3 13.7 1.0 15.8 ns
V
CC
= 2.3 V to 2.7 V 1.7 4.2 7.7 1.7 8.9 ns
V
CC
= 2.7 V 1.5 4.4 8.2 1.5 10.5 ns
V
CC
= 3.0 V to 3.6 V 1.5 3.8 6.9 1.5 9.0 ns
t
W
pulse width CP HIGH or LOW; see Figure 8
V
CC
= 1.65 V to 1.95 V 6.0 - - 6.0 - ns
V
CC
= 2.3 V to 2.7 V 5.0 - - 5.0 - ns
V
CC
= 2.7 V 5.0 - - 5.0 - ns
V
CC
= 3.0 V to 3.6 V 4.0 1.2 - 4.0 - ns
74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 11 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
t
su
set-up time Dn to CP; see Figure 11
V
CC
= 1.65 V to 1.95 V 5.5 - - 5.5 - ns
V
CC
= 2.3 V to 2.7 V 4.5 - - 4.5 - ns
V
CC
= 2.7 V 3.0 - - 3.0 - ns
V
CC
= 3.0 V to 3.6 V 2.5 1.0 - 2.5 - ns
PE
to CP; see Figure 11
V
CC
= 1.65 V to 1.95 V 4.5 - - 4.5 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.5 - - 3.5 - ns
V
CC
= 3.0 V to 3.6 V 3.0 1.2 - 3.0 - ns
U/D
to CP; see Figure 12
V
CC
= 1.65 V to 1.95 V 9.0 - - 9.0 - ns
V
CC
= 2.3 V to 2.7 V 7.0 - - 7.0 - ns
V
CC
= 2.7 V 6.5 - - 6.5 - ns
V
CC
= 3.0 V to 3.6 V 5.5 2.8 - 5.5 - ns
CEP
, CET to CP; see Figure 12
V
CC
= 1.65 V to 1.95 V 9.0 - - 9.0 - ns
V
CC
= 2.3 V to 2.7 V 6.0 - - 6.0 - ns
V
CC
= 2.7 V 5.5 - - 5.5 - ns
V
CC
= 3.0 V to 3.6 V 4.5 2.1 - 4.5 - ns
t
h
hold time Dn, PE, CEP, CET, U/D to CP;
see Figure 11
and 12
V
CC
= 1.65 V to 1.95 V 1.0 - - 1.0 - ns
V
CC
= 2.3 V to 2.7 V 1.0 - - 1.0 - ns
V
CC
= 2.7 V 0.0 - - 0.0 - ns
V
CC
= 3.0 V to 3.6 V 0.5 0.0 - 0.5 - ns
f
max
maximum
frequency
see Figure 8
V
CC
= 1.65 V to 1.95 V 100 - - 80 - MHz
V
CC
= 2.3 V to 2.7 V 125 - - 100 - MHz
V
CC
= 2.7 V 150 - - 120 - MHz
V
CC
= 3.0 V to 3.6 V 150 200 - 120 - MHz
t
sk(o)
output skew time V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC169 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 29 November 2012 12 of 24
NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volt
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of outputs
11. Waveforms
C
PD
power dissipation
capacitance
per input pin; V
I
= GND to V
CC
[4]
V
CC
= 1.65 V to 1.95 V - 12.7 - - - pF
V
CC
= 2.3 V to 2.7 V - 16.4 - - - pF
V
CC
= 3.0 V to 3.6 V - 19.7 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Measurement points are given in Table 8.
Logic levels: V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 8. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency
001aaa651
CP
input
Qn, TC
output
t
PHL
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M

74LVC169DB,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Counter ICs 3.3V SYNC 4-BIT BIN
Lifecycle:
New from this manufacturer.
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