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CY7C1041BNV33L-15VXCT

P1-P3P4-P6P7-P8
256K x 16 Static RAM
CY7C1041BNV33
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06434 Rev. ** Revised February 1, 2006
1CY7C1041BNV33
Features
•High speed
—t
AA
= 12 ns
• Low active power
— 612 mW (max.)
• Low CMOS standby power (Commercial L version)
— 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE features
Functional Description
The CY7C1041BNV33 is a high-performance CMOS Static
RAM organized as 262,144 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
(CE
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE
) and Output Enable (OE) LOW while forcing the
Write Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BNV33 is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
14
15
Logic Block Diagram Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K x 16
ARRAY
A
0
A
11
A
13
A
12
A
A
A
16
A
17
A
9
A
10
1024 x 4096
I/O
0
– I/O
7
OE
I/O
8
– I/O
15
CE
WE
BLE
BHE
Top View
SOJ
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
V
CC
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
I/O
15
A
2
CE
I/O
2
I/O
0
I/O
1
BHE
A
3
A
4
18
17
20
19
I/O
3
27
28
25
26
22
21
23
24
V
SS
I/O
6
I/O
4
I/O
5
I/O
7
A
16
A
15
BLE
V
CC
I/O
14
I/O
13
I/O
12
I/O
11
I/O
10
I/O
9
I/O
8
A
14
A
13
A
12
A
11
A
9
A
10
NC
CY7C1041BNV33
Document #: 001-06434 Rev. ** Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[1]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Selection Guide
-12 -15
Maximum Access Time (ns) 12 15
Maximum Operating Current (mA) Comm’l 190 170
Ind’l - 190
Maximum CMOS Standby Current (mA) Com’l/Ind’l 8 8
Com’l L0.5 0.5
Operating Range
Range
Ambient
Temperature
[2]
V
CC
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
-12 -15
Min. Max. Min. Max. Unit
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
= –4.0 mA 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+0.5 2.2 V
CC
+0.5 V
V
IL
Input LOW Voltage
[1]
–0.5 0.8 –0.5 0.8 V
I
IX
Input Leakage Current GND < V
I
< V
CC
–1 +1 –1 +1 mA
I
OZ
Output Leakage Current GND < V
OUT
< V
CC
, Output Disabled –1 +1 –1 +1 mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Comm’l 190 170 mA
Ind’l - 190 mA
I
SB1
Automatic CE Power-Down
Current —TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
40 40 mA
I
SB2
Automatic CE Power-Down
Current —CMOS Inputs
Max. V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,or
V
IN
< 0.3V, f = 0
Com’l/Ind’l 8 8 mA
Com’l L 0.5 0.5 mA
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V 8 pF
C
OUT
I/O Capacitance 8 pF
AC Test Loads and Waveforms
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
90%
10%
3.3V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
OUTPUT
(a)
(b)
R1 317Ω
167Ω
R2
351Ω
VENIN EQUIVALENT
THÉ
1.73V
Rise time: 1 V/ns
Fall time:
1 V/ns
CY7C1041BNV33
Document #: 001-06434 Rev. ** Page 3 of 8
Switching Characteristics
[4]
Over the Operating Range
-12 -15
Parameter Description Min. Max. Min. Max. Unit
READ CYCLE
t
RC
Read Cycle Time 12 15 ns
t
AA
Address to Data Valid 12 15 ns
t
OHA
Data Hold from Address Change 3 3 ns
t
ACE
CE LOW to Data Valid 12 15 ns
t
DOE
OE LOW to Data Valid 6 7 ns
t
LZOE
OE LOW to Low Z 0 0 ns
t
HZOE
OE HIGH to High Z
[5, 6]
67ns
t
LZCE
CE LOW to Low Z
[6]
33 ns
t
HZCE
CE HIGH to High Z
[5, 6]
67ns
t
PU
CE LOW to Power-Up 0 0 ns
t
PD
CE HIGH to Power-Down 12 15 ns
t
DBE
Byte Enable to Data Valid 6 7 ns
t
LZBE
Byte Enable to Low Z 0 0 ns
t
HZBE
Byte Disable to High Z 6 7 ns
WRITE CYCLE
[7, 8]
t
WC
Write Cycle Time 12 15 ns
t
SCE
CE LOW to Write End 10 12 ns
t
AW
Address Set-Up to Write End 10 12 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-Up to Write Start 0 0 ns
t
PWE
WE Pulse Width 10 12 ns
t
SD
Data Set-Up to Write End 7 8 ns
t
HD
Data Hold from Write End 0 0 ns
t
LZWE
WE HIGH to Low Z
[6]
33 ns
t
HZWE
WE LOW to High Z
[5, 6]
67ns
t
BW
Byte Enable to End of Write 10 12 ns
Data Retention Characteristics Over the Operating Range (For L version only)
Parameter Description Conditions
[10]
Min. Max. Unit
V
DR
V
CC
for Data Retention 2.0 V
I
CCDR
Data Retention Current V
CC
= V
DR
= 2.0V,
CE
> V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
330 µA
t
CDR
[3]
Chip Deselect to Data
Retention Time
0 ns
t
R
[9]
Operation Recovery Time t
RC
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE
LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
9. t
r
< 3 ns for the -12 and -15 speeds.
10.No input may exceed V
CC
+ 0.5V.
P1-P3P4-P6P7-P8

CY7C1041BNV33L-15VXCT

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Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 4M PARALLEL 44SOJ
Lifecycle:
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