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97U2A877AHLF

P1-P3P4-P6P7-P9P10-P12P13-P14
7
ICS97U2A877A
Advance Information
1180—11/14/05
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
Switching Characteristics
1
T
A
= 0 - 70°C Supply Volta
g
e AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION (MHz)
MIN TYP MAX UNITS
Output enable time
t
en
OE to any output 4.73 8 ns
Output disable time
t
dis
OE to any output 5.82 8 ns
160 to 270 -40 40
p
s
271 to 410 -30 30
p
s
160 to 270
-60 60
p
s
271 to 410 -50 50
p
s
In
p
ut Clock 1 2.5 4 v/ns
Output Enable (OE), (OS) 0.5 v/ns
Output clock slew rate
SLr1(o)
1.5 2.5 3 v/ns
t
jit(cc+)
040ps
t
jit(cc-)
0 -40 ps
160 to 270 -50 50
p
s
271 to 410
-20 20
p
s
Static Phase Offset
t
SPO
2
271 to 410 -50 0 50 ps
t
jit (per)
+
t
(Ø)dyn +
t
skew(o)
∑
(su)
80 ps
t
(
Ø
)
d
y
n
+
t
skew
o
∑
t
(
h
)
60 ps
160 to 270 40 ps
271 to 410 30
p
s
SSC modulation fre
q
uenc
y
30.00 33 kHz
SSC clock input frequency
deviation
0.00 -0.50 %
PLL Loop bandwidth (-3 dB
from unit
y
g
ain
)
2.0 MHz
Output to Output Skew
t
skew
160 to 410
Period jitter
t
jit (per)
Input slew rate
SLr1(i)
160 to 410
Cycle-to-cycle period jitter
Dynamic Phase Offset
t
(Ø)dyn
Half-period jitter
t
jit(hper)
8
ICS97U2A877A
Advance Information
1180—11/14/05
GND
ICS97U2A877A
V
DD
V
(CLKC)
V
(CLKC)
SCOPE
C=10pF
-VDD/2
GND
- GND
VDD/2
Z=6
Z = 2.97"
Z = 120Ω
Z = 2.97"
0Ω
Z=60Ω
Z=50Ω
Z=50Ω
R=10Ω
R=10Ω
V
(TT)
V
(TT)
C=10pF
Note: V
TT
= GND
t
c(n)
t
c(n+1)
t
jit(cc)
=t
c(n)
±t
c(n+1)
Figure 1. IBIS Model Output Load
Figure 2. Output Load Test Circuit
Y , FB_OUTC
X
Y , FB_OUTT
X
Parameter Measurement Information
ICS97U2A877A
Figure 3. Cycle-to-Cycle Jitter
R = 1MΩ
C = 1 pF
R = 1MΩ
C = 1 pF
9
ICS97U2A877A
Advance Information
1180—11/14/05
(N is a large number of samples)
t
( ) n+1
t
()n
t
()
=
1
n=
N
t
()n
N
CLK_INC
CLK_INT
FB_INC
FB_INT
t
(skew)
Y
#
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y , FB_OUTC
X
Y , FB_OUTT
X
Y
X
Parameter Measurement Information
Figure 4. Static Phase Offset
Figure 5. Output
Skew
1
f
O
t
=
t
-
(jit_per)
t
c(n)
C(n)
1
f
O
Figure 6. Period Jitter
P1-P3P4-P6P7-P9P10-P12P13-P14

97U2A877AHLF

Mfr. #:
Buy 97U2A877AHLF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1.8V LOW POWER WIDE RANGE
Lifecycle:
New from this manufacturer.
Delivery:
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