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ISL6115CBZA

P1-P3P4-P6P7-P9P10-P12P13-P14
4
FN9100.8
December 3, 2015
Absolute Maximum Ratings T
A
= +25°C Thermal Information
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +16V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+ 8V
ISEN, PGOOD, PWRON, CTIM, ISET . . . -0.3V to V
DD
+ 0.3V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . 5kV
Operating Conditions
V
DD
Supply Voltage Range (ISL6115). . . . . . . . +12V ±15%
V
DD
Supply Voltage Range (ISL6116, 17, 20) . . +12V ±25%
Temperature Range (T
A
) . . . . . . . . . . . . . . . . 0°C to +85°C
Thermal Resistance (Typical, Note 4)
JA
(°C/W)
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . 98
Maximum Junction Temperature (Plastic Package) . . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications V
DD
= 12V, T
A
= T
J
= 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNITS
CURRENT CONTROL
ISET Current Source I
ISET_ft
18.5 20 21.5 µA
ISET Current Source I
ISET_pt
T
J
= +15°C to +55°C 19 20 21 µA
Current Limit Amp Offset Voltage Vio_ft V
ISET
- V
ISEN
-6 0 6 mV
Current Limit Amp Offset Voltage Vio_pt V
ISET
- V
ISEN,
T
J
= +15°C to
+55°C
-2 0 2 mV
GATE DRIVE
GATE Response Time to Severe OC pd_woc_amp V
GATE
to 10.8V - 100 - ns
GATE Response Time to Overcurrent pd_oc_amp V
GATE
to 10.8V - 600 - ns
GATE Turn-On Current I
GATE
V
GATE
to = 6V 8.4 10 11.6 µA
GATE Pull-Down Current OC_GATE_I_4V Overcurrent 45 75 - mA
GATE Pull-Down Current (Note 6) WOC_GATE_I_4V Severe Overcurrent 0.5 0.8 - A
ISL6115 Undervoltage Threshold 12V
UV_VTH
9.2 9.6 10 V
ISL6115 GATE High Voltage 12VG GATE Voltage V
DD
+ 4.5V V
DD
+ 5V - V
ISL6116 Undervoltage Threshold 5V
UV_VTH
4.0 4.35 4.5 V
ISL6117 Undervoltage Threshold 3V
UV_VTH
2.4 2.6 2.8 V
ISL6120 Undervoltage Threshold 2V
UV_VTH
1.8 1.85 1.9 V
ISL6116, ISL6117, ISL6120 GATE
High Voltage
VG GATE Voltage V
DD
- 1.5V V
DD
- V
BIAS
V
DD
Supply Current I
VDD
- 3 5 mA
V
DD
POR Rising Threshold V
DD_POR_L2H
VDD Low to High 7.8 8.4 9 V
V
DD
POR Falling Threshold V
DD_POR_H2L
VDD High to Low 7.5 8.1 8.7 V
V
DD
POR Threshold Hysteresis V
DD_POR_HYS
V
DD_POR_L2H -
V
DD_POR_H2L
0.1 0.3 0.6 V
Maximum PWRON Pull-Up Voltage PWRN_PUV Maximum External Pull-up
Voltage
- 5 - V
ISL6115, ISL6116, ISL6117, ISL6120
5
FN9100.8
December 3, 2015
Description and Operation
The members of this IC family are single power supply
distribution controllers for generic hot swap
applications across the +2.5V to +12V supply range.
The ISL6115 is targeted for +12V switching
applications whereas the ISL6116 is targeted for +5V,
the ISL6117 for +3.3V and the ISL6120 for +2.5V
applications. Each IC has a hardwired undervoltage
(UV) threshold level approximately 17% lower than the
stated voltages.
These ICs feature a highly accurate programmable
current regulation (CR) level with programmable time
delay to latch-off, and programmable soft-start
turnHon ramp all set with a minimum of external
passive components. The ICs also include severe OC
protection that immediately shuts down the MOSFET
switch should a rapid load current transient such as
with a dead short cause the CR Vth to exceed the
programmed level by 150mV. Additionally, the ICs
have a UV indicator and an OC latch indicator. The
functionality of the PGOOD feature is enabled once
the IC is biased, monitoring and reporting any UV
condition on the ISEN pin.
Upon initial power-up, the IC can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switch off or apply the supply rail
voltage directly to the load for true hot swap capability.
The PWRON pin must be pulled low for the device to
isolate the power supply from the load by holding the
external N-Channel MOSFET off. With the PWRON pin
held high or floating the IC will be in true hot swap
mode. In both cases the IC turns on in a soft-start
mode protecting the supply rail from sudden in-rush
current.
At turn-on, the external gate capacitor of the N-
Channel MOSFET is charged with a 10µA current
source resulting in a programmable ramp (soft-start
turn-on). The internal ISL6115 charge pump supplies
the gate drive for the 12V supply switch driving that
gate to ~V
DD
+5V, for the other three ICs the gate
drive voltage is limited to the chip bias voltage, VDD.
Load current passes through the external current
sense resistor. When the voltage across the sense
resistor exceeds the user programmed CR voltage
threshold value, (see Table 1 for R
ISET
programming
resistor value and resulting nominal current regulation
threshold voltage, V
CR
) the controller enters its
current regulation mode. At this time, the time-out
capacitor, on CTIM
pin is charged with a 20µA current
source and the controller enters the current limit time
to latch-off period. The length of the current limit time
to latch-off duration is set by the value of a single
external capacitor (see Table 2) for C
TIM
capacitor
value and resulting nominal current limited time-out
to latch-off duration placed from the CTIM pin (pin 6)
to ground. The programmed current level is held until
either the OC event passes or the time-out period
expires. If the former is the case then the N-Channel
MOSFET is fully enhanced and the C
TIM
capacitor is
discharged. Once C
TIM
charges to 1.87V signaling
that the time-out period has expired, an internal latch
is set whereby the FET gate is quickly pulled to 0V
turning off the N-Channel MOSFET switch, isolating
the faulty load.
PWRON Pull-Up Voltage PWRN_V PWRON Pin Open 2.7 3.2 - V
PWRON Rising Threshold PWR_Vth 1.4 1.7 2.0 V
PWRON Hysteresis PWR_hys 130 170 250 mV
PWRON Pull-Up Current PWRN_I 9 17 25 µA
CURRENT REGULATION DURATION/POWER GOOD
C
TIM
Charging Current C
TIM
_ichg0 V
CTIM
= 0V 16 20 23 µA
C
TIM
Fault Pull-Up Current (Note 6) - 20 - mA
Current Limit Time-Out Threshold
Voltage
C
TIM
_Vth CTIM Voltage 1.3 1.8 2.3 V
Power Good Pull Down Current PG_Ipd V
OUT
= 0.5V - 8 - mA
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Electrical Specifications V
DD
= 12V, T
A
= T
J
= 0°C to +85°C, Unless Otherwise Specified. Temperature limits
established by characterization and are not production tested. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNITS
ISL6115, ISL6116, ISL6117, ISL6120
6
FN9100.8
December 3, 2015
This IC responds to a severe overcurrent load (defined
as a voltage across the sense resistor >150mV over
the OC Vth set point) by immediately driving the
N-Channel MOSFET gate to 0V in about 10µs. The gate
voltage is then slowly ramped up turning on the
N-Channel MOSFET to the programmed current
regulation level; this is the start of the time-out period.
Upon a UV condition, the PGOOD signal will pull low
when tied high through a resistor to the logic or VDD
supply. This pin is a UV fault indicator. For an OC
latch-off indication, monitor CTIM, pin 6. This pin will
rise rapidly from 1.9V to VDD once the time-out period
expires.
See Figures 12 through 16 for waveforms relevant to
text.
The IC is reset after an OC latch-off condition by a low
level on the PWRON pin and is turned on by the
PWRON pin being driven high.
Application Considerations
Design applications where the CR Vth is set extremely
low (25mV or less), there is a two-fold risk to
consider.
• There is the susceptibility to noise influencing the
absolute CR Vth value. This can be addressed with a
100pF capacitor across the R
SENSE
resistor.
• Due to common mode limitations of the
overcurrent comparator, the voltage on the ISET
pin must be 20mV above the IC ground either
initially (from I
SET
*R
SET
) or before C
TIM
reaches
time-out (from gate charge-up). If this does not
happen, the IC may incorrectly report overcurrent
fault at start-up when there is no fault. Circuits
with high load capacitance and initially low load
current are susceptible to this type of unexpected
behavior.
Do not signal nor pull-up the PWRON input to > 5V.
Exceeding 6V on this pin will cause the internal charge
pump to malfunction.
During the soft-start and the time-out delay duration
with the IC in its current limit mode, the V
GS
of the
external N-Channel MOSFET is reduced driving the
MOSFET switch into a (linear region) high r
DS(ON)
state. Strike a balance between the CR limit and the
timing requirements to avoid periods when the
external N-Channel MOSFETs may be damaged or
destroyed due to excessive internal power dissipation.
Refer to the MOSFET SOA information in the
manufacturer’s data sheet.
When driving particularly large capacitive loads a
longer soft-start time to prevent current regulation
upon charging and a short CR time may offer the best
application solution relative to reliability and FET MTF.
Physical layout of R
SENSE
resistor is critical to
avoid the possibility of false overcurrent occurrences.
Ideally, trace routing between the R
SENSE
resistors
and the IC is as direct and as short as possible with
zero current in the sense lines (see Figure 1)..
Using the ISL6116 as a -48V
Low Side Hot Swap Power
Controller
To supply the required V
DD
, it is necessary to maintain
the chip supply 10V to 16V above the -48V bus. This
may be accomplished with a suitable regulator
between the voltage rail and pin 5 (VDD). By using a
regulator, the designer may ignore the bus voltage
variations. However, a low-cost alternative is to use a
Zener diode (see Figure 2 for typical 5A load control);
this option is detailed in the following.
Note that in this configuration the PGOOD feature
(pin 7) is not operational as the I
SEN
pin voltage is
always < UV threshold.
See Figures 17 through 20 for waveforms relevant to
-48V and other high voltage applications.
TABLE 1. R
ISET
PROGRAMMING RESISTOR VALUE
R
ISET
RESISTOR NOMINAL CR VTH
10k 200mV
4.99k 100mV
2.5k 50mV
750 15mV
NOTE: Nominal Vth = R
ISET
x 20µA.
TABLE 2. C
TIM
CAPACITOR VALUE
C
TIM
CAPACITOR
NOMINAL CURRENT LIMITED
PERIOD
0.022µF 2ms
0.047µF 4.4ms
0.1µF 9.3ms
NOTE: Nominal time-out period = C
TIM
x 93k.
CORRECT
TO ISEN AND
CURRENT
SENSE RESISTOR
INCORRECT
FIGURE 1. SENSE RESISTOR PCB LAYOUT
R
ISET
ISL6115, ISL6116, ISL6117, ISL6120
P1-P3P4-P6P7-P9P10-P12P13-P14

ISL6115CBZA

Mfr. #:
Buy ISL6115CBZA
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers W/ANNEAL 8LD +12V HOT PLUG CNTRLR
Lifecycle:
New from this manufacturer.
Delivery:
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