527R-02LF Datasheet 527R-02LFT, 527R-02LF, 527R-02ILF | P1-P3

DATASHEET

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER

ICS527-02

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 1

ICS527-02 REV J 051310

Description

The ICS527-02 Clock Slicer is the most flexible way to

generate a CMOS output clock from a PECL input

clock with zero skew. The user can easily configure the

device to produce nearly any output clock that is

multiplied or divided from the input clock. The part

supports non-integer multiplications and divisions. A

SYNC pulse indicates when the rising clock edges are

aligned with zero skew. Using Phase-Locked Loop

(PLL) techniques, the device accepts an input clock up

to 200 MHz and produces an output clock up to 160

MHz.

The ICS527-02 aligns rising edges on PECLIN with

FBIN at a ratio determined by the reference and

feedback dividers.

For a PECL input and output clock with zero delay, use

the ICS527-04.

For a CMOS input and PECL output with zero delay,

use the ICS527-03.

Features

• Packaged as 28-pin SSOP, Pb-free (150 mil body)

• Synchronizes fractional clocks rising edges

• PECL IN to CMOS OUT

• Pin selectable dividers

• Zero input to output skew

• User determines the output frequency—no software

needed

• Slices frequency or period

• Input clock frequency of 1.5 MHz to 200 MHz

• Output clock frequencies from 4 MHz to 160 MHz

• Very low jitter

• Duty cycle of 45/55

• Operating voltage of 3.3 V

• Advanced, low-power CMOS process

• Industrial temperature version available

Block Diagram

PECLIN

VDD

GND

CLK1

CLK2

Reference

Divider

PECLIN

Phase Comparator,

Charge Pump, and

Loop Filter

VCO

Output

Divider

R6:R0

F6:F0 S1:S0

PDTS

Feedback

Divider

FBIN

Divide

by 2

SYNC

DIV2

Feedback can

come from

CLK1 or CLK2

(not both)

33 ohm

ICS527-02

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 2

ICS527-02 REV J 051310

Pin Assignment

28-pin 150 mil body SSOP

Output Frequency Range Table

CLK2 Operation Table

Pin Descriptions

PECLIN

GND

CLK2

OECLK2

GND

PDTS

FBIN

CLK1

VDD

DIV2

S1 S0 Output Frequency (MHz)

Commercial Industrial

0 0 10 - 50 16 - 45

0 1 5 - 40 8 - 33

1 0 4 - 10 4 - 8

1 1 20 -160 32 - 140

OECLK2 DIV2 CLK2

0X Z

1 0 SYNC

11 CLK1/2

Number

Name

Type

Pin Description

1,2, 24-28 R5, R6,

R0-R4

Input Reference divider word input pins determined by user. Forms a binary number

from 0 to 127. Internal pull-up.

3 DIV2 Input Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based

on the table above. Internal pull-up.

4, 5 S0, S1 Input Select pins for output divider determined by user. See table above. Internal

pull-up.

6, 23 VDD Power Connect to +3.3 V.

7 PECLIN Input True PECL input clock.

8 PECLIN Input Complementary PECL input clock.

9, 20 GND Power Connect to ground

10 OECLK2 Input CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up.

11-17 F0-F6 Input Feedback divider word input pins determined by user. Forms a binary number

from 0 to 127. Internal pull-up

18 FBIN Input Feedback clock input

19 PDTS

Input Power Down. Active low. Turns off entire chip when low, both clock outputs are

tri-stated. Internal pull-up.

21 CLK2 Output Output clock 2. Can be SYNC pulse or a low skew divide by 2 of CLK1.

22 CLK1 Output Output clock 1.

ICS527-02

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 3

ICS527-02 REV J 051310

External Components

Decoupling Capacitors

As with any high performance mixed-signal IC, the

ICS527-02 must be isolated from system power supply

noise to perform optimally.

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane. The

capacitor must be connected close to the device to

minimize lead inductance.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50Ω trace (a

commonly used trace impedance), place a 33Ω resistor

in series with the clock line, as close to the clock output

pin as possible. The nominal impedance of the clock

output is 20Ω.

Using the ICS527-02 Clock Slicer

First use DIV2 to select the function of the CLK2 output.

If DIV2 is high, a divide by 2, low skew version of CLK1

is present on CLK2. If DIV2 is low, a SYNC pulse is

generated on CLK2. The SYNC pulse goes high

synchronously with the rising edges of PECLIN and

CLK1 that are de-skewed. The SYNC function operates

at CLK1 frequencies up to 66 MHz. If neither CLK1/2 or

a SYNC pulse are required, then CLK2 should be

disabled by connecting OECLK2 to ground. This will

also give the lowest jitter on CLK1.

Next, the feedback scheme should be chosen. If CLK2

is being used as a SYNC pulse, or is tri-stated, then

CLK1 must be connected to FBIN. If CLK2 is selected

to be CLK1/2 (DIV2=1, OECLK2=1) then either CLK1 or

CLK2 must be connected to FBIN. The choice between

CLK1 or CLK2 is illustrated by the following examples

where the device has been configured to generate

CLK1 that is twice the frequency on PECLIN.

Using CLK1 as feedback will always result in

synchronized rising edges between PECLIN and CLK1

if CLK1 is used as feedback. CLK2 could be a falling

edge compared to PECLIN. Therefore, wherever

possible it is recommended to use CLK2 for feedback,

which will synchronize the rising edges of all three

clocks.

More complicated feedback schemes can be used,

such as incorporating multiple output buffers in the

feedback path. An example is given later in the

datasheet. The fundamental property of the ICS527-02

is that it aligns rising edges on PECLIN and FBIN at a

ratio determined by the reference and feedback

dividers.

Set S1 and S0 (page 2) based on the output frequency.

Lastly, the divider settings should be selected. This is

described in the following section.

Determining ICS527-02 Divider Settings

The user has full control in setting the desired output

clock over the range shown in the table on page 2. The

user should connect the divider select input pins directly

to ground (or VDD, although this is not required

PECLIN

CLK1 Feedback

CLK1

CLK2

phase is

ind ete rm ina te

PECLIN

CLK1

CLK2

CLK2 Feedback

PECLIN

P1-P3 P4-P6 P7-P9 P10-P10

527R-02LF

Mfr. #:

Buy 527R-02LF

Manufacturer:

IDT

Description:

Clock Buffer CLOCK SLICER CONFIGURABLE BUFFER

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

527R-02LF

527R-02LF

Products related to this Datasheet