527R-02LFT Datasheet 527R-02LFT, 527R-02LF, 527R-02ILF | P4-P6

ICS527-02

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 4

ICS527-02 REV J 051310

because of internal pull-ups) during Printed Circuit

Board layout, so the ICS527-02 automatically produces

the correct clock when mounted on the board. It is also

possible to connect the inputs to parallel I/O ports in

order to switch frequencies.

The output of the ICS527-02 can be determined by the

following simple equation:

Where:

Reference Divider Word (RDW) = 0 to 127

Feedback Divider Word (FDW) = 0 to 127

FB Frequency is the same as either CLK1 or

CLK2 depending on feedback connection

Also, the following operating ranges should be

observed:

S0 and S1 should be selected depending on the

frequency of CLK1. The table on page 2 gives the

ranges.

The dividers are expressed as integers. For example, if

a 50 MHz output on CLK1 is desired from a 40 MHz

input, the reference divider word (RDW) should be 2

and the feedback divider word (FDW) should be 3 which

gives the required 5/4 multiplication. If multiple choices

of dividers are available, then the lowest numbers

should be used. In this example, the output divide (OD)

should be selected to be 2. Then R6:R0 is 0000010,

F6:F0 is 0000011 and S1:S0 is 00. Also, this example

assumes CLK1 is connected to FBIN.

If you need assistance determining the optimum divider

settings, please send an e-mail to

mk-support@icst.com with the desired input clock and

the desired output frequency.

Typical Example

The layout diagram below will produce the waveforms shown on the right.

Note: The series termination resistor is located before the feedback trace.

FB Frequency

Input Frequency

FDW 2+

RDW 2+

------------------------

×=

300kHz

Input Frequency

RDW 2+

-------------------------------------------

20 MHz<<

40 MHz

PECLIN

50 MHz

CLK1

SYNC

CLK2

PECLIN

FBIN

PECLIN

GND

OECLK2

CLK1

CLK2

GND

VDD

DIV2

PECLIN

PDTS

50 MHz

SYNC

33Ω

0.01µF

40 MHz

0.01µF

VDD

ICS527-02

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 5

ICS527-02 REV J 051310

Multiple Output Example

In this example, an input clock of 125 MHz is used. Eight copies of 50 MHz are required as are eight copies

of 25 MHz, de-skewed and aligned to the 125 MHz input clock. The following solution uses the

MK74CB217 which has dual 1 to 8 buffers with low pin-to-pin skew.

PCB Layout Recommendations

For optimum device performance and lowest output

phase noise, the following guidelines should be

observed.

1) Each 0.01µF decoupling capacitor should be

mounted on the component side of the board as close

to the VDD pin as possible. No via’s should be used

between decoupling capacitor and VDD pin. The PCB

trace to VDD pin should be kept as short as possible, as

should the PCB trace to the ground via.

2) To minimize EMI the 33Ω series termination resistor,

if needed, should be placed close to the clock outputs.

3) An optimum layout is one with all components on the

same side of the board, minimizing vias through other

signal layers. Other signal traces should be routed away

from the ICS527-02. This includes signal traces just

underneath the device, or on layers adjacent to the

ground plane layer used by the device.

FBIN

PECLIN

GND

OECLK2

CLK1

CLK2

GND

VDD

DIV2

PECLIN

PDTS

0.01µF

125 MHz

0.01µF

VDD

QB5

QA3

QB6

QB7

OEB

GND

QA5

QA6

QA7

OEA

QB3

QB4

GND

VDD

QA1

QA2

QB1

QB2

INA

QA0

INB

QB0

QA4

GND

0.01µF

MK74CB217

ICS527-02

The layout design above produces the waveforms shown below. Note: Series terminating resistors are not shown.

25M

50M

125 MHz,

PECLIN

25 MHz,

QA0-7

50 MHz,

QB0-7

PECLIN not shown

ICS527-02

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER PECL ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™

CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER 6

ICS527-02 REV J 051310

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS527-02. These ratings,

which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Recommended Operation Conditions

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C

Item Rating

Supply Voltage, VDD 7 V

All Inputs and Outputs -0.5 V to VDD+0.5 V

Ambient Operating Temperature -40 to +85° C

Storage Temperature -65 to +150° C

Junction Temperature 125° C

Soldering Temperature 260° C

Parameter Min. Typ. Max. Units

Ambient Operating Temperature, ICS527R-02 0 – +70 ° C

Ambient Operating Temperature, ICS527R-02I -40 – +85 ° C

Power Supply Voltage (measured in respect to GND) +3.135 +3.3 +3.465 V

Parameter Symbol Conditions Min. Typ. Max. Units

Operating Voltage VDD 3.135 3.3 3.465 V

Supply Current IDD 15 MHz in, 60 MHz

out, no load

18 mA

Supply Current, Power Down IDDPD PDTS

=0 20 µA

Input High Voltage V

Input Low Voltage V

0.8 V

Input Voltage, peak-to-peak PECLIN, PECLIN

0.3 1 V

Common Mode Range PECLIN, PECLIN

VDD-1.4 VDD-0.6 V

Output High Voltage V

= -12 mA 2.4 V

Output Low Voltage V

= 12 mA 0.4 V

P1-P3 P4-P6 P7-P9 P10-P10

527R-02LFT

Mfr. #:

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Manufacturer:

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Description:

Clock Buffer CLOCK SLICER CONFIGURABLE BUFFER

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527R-02LFT

527R-02LFT

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