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HMC8120

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
HMC8120 Data Sheet
Rev. A | Page 12 of 16
THEORY OF OPERATION
The circuit architecture of the HMC8120 variable gain amplifier
is shown in Figure 37. The HMC8120 uses multiple gain stages
and staggered voltage variable attenuation stages to form a low
noise, high linearity variable gain amplifier with a gain range of
~15 dB. The first stage is a low noise preamp, which is followed
by the first voltage variable attenuator in the signal path. A
portion of the signal is coupled away and further amplified
before driving an on-chip envelope detector. The envelope
detector provides an output that is proportional to the peak
envelope power of the incoming signal. After the first
attenuator, a second stage amplifier provides additional gain
and isolation before driving the second variable attenuator
block. Three cascaded gain stages follow the second variable
attenuator. At the output of the last stage, another coupler taps
off a small portion of the output signal. The coupled signal is
presented to an on-chip diode detector for external monitoring
of the output power. A matched reference diode is included to
help correct for detector temperature dependencies. See the
application circuit in Figure 38 for further details on biasing the
different blocks and utilizing the detector features.
RFIN
RFOUT
ENV
DET
ENV
DET
V
CTL1
V
CTL2
V
REF
V
DET
13150-034
Figure 37. Variable Gain Amplifier Circuit Architecture
Data Sheet HMC8120
Rev. A | Page 13 of 16
TYPICAL APPLICATION CIRCUIT
A typical application circuit for the HMC8120 is provided in
Figure 38. For typical operation, drive the attenuator control
pads from a single control voltage. It is important to bypass all
the supply connections and attenuator control pads with adequate
bypassing capacitors. Use single-layer chip capacitors with very
high self-resonant frequency close to the HMC8120 die, bypassing
each supply or control pad. Typically, 120 pF chip capacitors are
used, followed by 0.01 μF and 4.7 μF surface-mount capacitors.
Combine supply lines as shown in the application circuit schematic
to minimize external component count and simplify power
supply routing (see Figure 38). Pad 25 and Pad 26 are internally
connected. Therefore, use either pad to connect the external
bypass components of V
DD1
/V
DD2
.
The HMC8120 uses several amplifier, detector, and attenuator
stages. All stages use depletion mode pHEMT transistors. It is
important to follow the following power-up bias sequence to
ensure transistor damage does not occur.
1. Apply a −5 V bias to the V
CTL1
and V
CTL2
pads.
2. Apply a −2 V bias to the V
GG3
to V
GG6
and V
GG1
/V
GG2
pads.
3. Apply 4 V to the V
DD1
to V
DD6
pads.
4. Adjust V
GG1
/V
GG2
and V
GG3
to V
GG6
between −2 V and 0 V
to achieve a total amplifier drain current of 250 mA.
After bias is established, adjust the V
CTL1
= V
CTL2
bias between
−5 V and 0 V to achieve the desired gain.
To p ower down the HMC8120, follow the reverse procedure.
For additional guidance on general bias sequencing, see the
MMIC Amplifier Biasing Procedure application note.
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
RFIN
V
GG1
/V
GG2
V
DD1
V
DD2
ENV
DET
V
CTL1
V
CTL2
V
GG3
V
DD3
V
GG4
V
DD4
V
GG5
V
GG6
V
DD5
V
DD6
V
REF
V
DET
1.6kΩ
1.6kΩ
123
4
5
6
RFOUT
120pF
0.01µF
4.7µF
120pF
0.01µF
4.7µF
V
GG1
/V
GG2
120pF 120pF120pF 120pF
0.01µF
4.7µF
V
GG3
,V
GG4
120pF
0.01µF
4.7µF
100kΩ
10kΩ 10kΩ
100kΩ
10kΩ
V
OUT
=V
REF
–V
DET
10kΩ
SUGGESTED CIRCUIT
+5V
+5V
–5V
V
DD6
V
REF
V
DET
120pF
0.01µF
4.7µF
V
DD3
,V
DD4
,V
DD5
0.01µF
4.7µF
V
GG5
,V
GG6
120pF
120pF 120pF
V
DD1
,V
DD2
120pF
0.01µF
4.7µF
V
CTL1
,V
CTL2
1000pF
ENV
DET
+4V
3.5kΩ
150Ω
HMC8120
13150-035
Figure 38. Typical Application Circuit
HMC8120 Data Sheet
Rev. A | Page 14 of 16
ASSEMBLY DIAGRAM
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
RFIN
V
GG1
/V
GG2
V
DD1
V
DD2
ENV
DET
V
CTL1
V
CTL2
V
GG3
V
DD3
V
GG4
V
DD4
V
GG5
V
GG6
V
DD5
V
DD6
V
REF
V
DET
1.6kΩ
1.6kΩ
123
4
5
6
RFOUT
3mil WIDE
GOLD RIBBON
(WEDGE BOND)
3mil WIDE
GOLD RIBBON
(WEDGE BOND)
120pF
0.01µF
3mil
NOMINAL
GAP
50Ω
TRANSMISSION
LINE
4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF 4.7µF
V
GG1
/V
GG2
V
GG3
, V
GG4
V
DD6
V
DD3
, V
DD4
, V
DD5
V
GG5
, V
GG6
V
DD1
, V
DD2
V
CTL1
, V
CTL2
HMC8120
13150-036
Figure 39. Assembly Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

HMC8120

Mfr. #:
Buy HMC8120
Manufacturer:
Analog Devices Inc.
Description:
RF Amplifier Analog VGA
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