DS1212
7 of 7
TYPICAL APPLICATION Figure 2
OUTPUT LOAD Figure 3
NOTES:
1. All voltages referenced to ground.
2. Only one battery input is required.
3. Measured with V
CCO
and CE0 -CE15 open.
4. I
CC01
is the maximum average load which the DS1212 can supply to the memories.
5. Measured with a load as shown in Figure 3.
6. I
CC02
is the maximum average load current which the DS1212 can supply to the memories in the battery backup
mode.
7. Chip enable outputs
CE0 -CE15 can only sustain leakage current in the battery backup mode.
8. t
CE
max. must be met to ensure data integrity on power loss.
9. t
AS
is only required to keep the decoder outputs glitch-free. While CE is low, the outputs (CE0 -CE15) will be
defined by inputs A through D with a propagation delay of t
PD
from an A through D input change.
10. For applications where higher currents are required, please see the Battery Manager chip data sheet (DS1259).
11. The DS1212 has a 5 kohm resistor in series with the battery input. As current from the battery increases over
100 µA, the voltage drop will increase proportionately. The device cannot be damaged by higher currents in the
battery path.
