MT8815 Data Sheet
7
Zarlink Semiconductor Inc.
† Timing is over recommended temperature range. See Fig. 3 for control and I/O timing details.
Digital Input rise time (tr) and fall time (tf) = 5ns.
‡ Typical figures are at 25
C and are for design aid only; not guaranteed and not subject to production testing.
1 Refer to Appendix, Fig. A.7 for test circuit.
Figure 3 - Control Memory Timing Diagram
* See Appendix, Fig. A.7 for switching waveform
AC Electrical Characteristics
†
- Control and I/O Timings- Voltages are with respect to V
DD
=5V, V
SS
=0V,
V
EE
=-7V, unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 Control Input crosstalk to switch
(for DATA, STROBE, Address)
CX
talk
30 mVpp V
IN
=3V squarewave;
R
IN
=1k, R
L
=10k.
See Appendix, Fig. A.6
2 Digital Input Capacitance C
DI
10 pF f=1MHz
3 Switching Frequency F
O
20 MHz
4 Setup Time DATA to STROBE t
DS
10 ns R
L
= 1k, C
L
=50pF
5 Hold Time DATA to STROBE t
DH
10 ns R
L
= 1k, C
L
=50pF
1
6 Setup Time Address to STROBE t
AS
10 ns R
L
= 1k, C
L
=50pF
1
7 Hold Time Address to STROBE t
AH
10 ns R
L
= 1k, C
L
=50pF
1
8 STROBE Pulse Width t
SPW
20 ns R
L
= 1k, C
L
=50pF
1
9 RESET Pulse Width t
RPW
40 ns R
L
= 1k, C
L
=50pF
1
10 STROBE to Switch Status Delay t
S
40 100 ns R
L
= 1k, C
L
=50pF
1
11 DATA to Switch Status Delay t
D
50 100 ns R
L
= 1k, C
L
=50pF
1
12 RESET to Switch Status Delay t
R
35 100 ns R
L
= 1k, C
L
=50pF
1
t
RPW
t
SPW
t
AS
t
AH
t
DH
t
D
t
S
t
R
t
R
t
DS
50% 50%
50%50%50%
50% 50%
50% 50%
RESET
STROBE
ADDRESS
DATA
SWITCH*
ON
OFF
