ADF4360-7 Data Sheet
Rev. E | Page 12 of 28
After band selection, normal PLL action resumes. The value of
K
V
is determined by the value of inductors used (see the Choosing
the Correct Inductance section). If divide-by-2 operation has
been selected (by programming DIV2 [DB22] high in the N
counter latch), the value is halved. The ADF4360-7 contains
linearization circuitry to minimize any variation of the product
of I
CP
and K
V
.
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RF
OUT
A and RF
OUT
B pins of the ADF4360-7 are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 21. To allow the user to
optimize the power dissipation vs. the output power require-
ments, the tail current of the differential pair is programmable
via Bits PL1 and PL2 in the control latch. Four current levels
may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These levels give
output power levels of −14 dBm, −11 dBm, −8 dBm, and −5 dBm,
respectively, using a 50 Ω resistor to V
DD
and ac coupling into a
50 Ω load. Alternatively, both outputs can be combined in a
1 + 1:1 transformer or a 180° microstrip coupler (see the
Output Matching section).
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
DD
.
Another feature of the ADF4360-7 is that the supply current
to the RF output stage is shut down until the device achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
VCO
RF
OUT
A RF
OUT
B
BUFFER/
DIVIDE BY 2
04441-021
Figure 21. Output Stage ADF4360-7
