LT6650CS5#TRPBF

LT6650
10
6650fa
APPLICATIO S I FOR ATIO
WUU
U
Figure 11. Worst-Case 0°C to 70°C Hysteresis Figure 12. Worst-Case –40°C to 85°C Hysteresis
V
OUT
. R
B
must be within the following range for proper
operation (the optimal value depends greatly on the direc-
tion and magnitude of the load current):
R
B
> |V
S
– V
OUT
|/(200µA + 0.4/R
G
)
R
B
< |V
S
– V
OUT
|/(15µA + 0.4/R
G
)
Hysteresis
Due to various mechanical stress mechanisms inherent to
integrated-circuit packaging, internal offsets may not pre-
cisely recover from variations that occur over tempera-
ture, and this effect is referred to as hysteresis. Proprietary
manufacturing steps minimize this hysteresis, though
some small residual error can occur. Hysteresis measure-
ments for the LT6650 can be seen in Figures 11 and 12.
Figure 11 presents the worst-case data taken on parts
subjected to thermal cycling between 0°C to 70°C, while
Figure 12 shows data for –40°C to 85°C cycling. Units
were cycled several times over these temperature ranges
and the largest changes are shown. As would be expected,
the parts cycled over the higher temperature extremes
exhibit a broader hysteresis distribution. The worst hys-
teresis measurements indicate voltage shifts of less than
1000ppm (0.1%) from their initial value.
Limits of Operation
The LT6650 is a robust bipolar technology part. ESD
clamp diodes are integrated into the design and are
depicted in the Simplified Schematic for reference. Diodes
are included between the GND pin and the IN, OUT, and FB
pins to prevent reverse voltage stress on the device.
Unusual modes of operation that forward-bias any these
diodes should limit current to 10mA to avoid permanent
damage to the device. The LT6650 is fabricated using a
relatively high-voltage process, allowing any pin to inde-
pendently operate at up to 20V with respect to GND. The
part does not include any over voltage protection mecha-
nisms; therefore caution should be exercised to avoid
inadvertent application of higher voltages in circuits in-
volving high potentials.
DISTRIBUTION (ppm)
–400
NUMBER OF UNITS
2
3
6
5
4
400
6650 F11
1
0
–200
0
200
600
LIGHT COLUMNS 0°C TO 25°C
DARK COLUMNS 70°C TO 25°C
DISTRIBUTION (ppm)
–1000
NUMBER OF UNITS
2
3
6
5
4
500
6650 F12
7
1
0
–500
1000
250
–750
–250
0
750
LIGHT COLUMNS –40°C TO 25°C
DARK COLUMNS 85°C TO 25°C
LT6650
11
6650fa
PACKAGE DESCRIPTIO
U
SCHE ATIC
WW
SI PLIFIED
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302 REV B
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635 Rev B)
IN
FB
GND
OUT
6650 SS
4
5
2
1
IN
ININ
LT6650
12
6650fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
LT/LT 1005 • PRINTED IN USA
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ANODE
CATHODE
ANODE
CATHODE
6650 TA02
10µF
1.4V V
Z
18V
30µA I
Z
220µA
V
Z
= 0.4V • (1 + R
F
/R
G
)
=
OUTIN
FB
GND
LT6650
2
45
1
R
F
R
G
1nF
Adjustable Micropower “Zener” 2-Terminal Reference

LT6650CS5#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Voltage References uP, 400mV Ref w/ R2R Buf Amp in SOT-23
Lifecycle:
New from this manufacturer.
Delivery:
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