2
QUALITY AND RELIABILITY
IXYS is committed to setting a new standard for
excellence in Power Semiconductors. Reflecting our
dedication to industry leadership in the manufacture of
medium to high power devices, reliability has
assumed a primary position in raw material selection,
design, and process technology.
Reliability utilizes information derived from applied
research, engineering design, analysis of field
applications and accelerated stress testing and
integrates this knowledge to optimize device design
and manufacturing processes.
All areas that impact reliability have received
considerable attention in order to achieve our goal to
be the # 1 Reliability Supplier of Power
Semiconductor products. We believe IXYS products
should be the most reliable components in your
system.
We have committed significant resources to
continuously improve and optimize our device design,
wafer fab processes, assembly processes and test
capabilities. As a result of this investment, IXYS has
realized a dramatic improvement in reliability
performance on all standardized tests throughout the
product line.
Excellence in product reliability is “built-in”, not tested-
in. Moreover, it requires a total systems approach,
involving all parties: from design to raw materials to
manufacturing.
In addition to qualifying new products released to the
market, life and environmental tests are periodically
performed on standard products to maintain feedback
on assembly and fabrication performance to assure
product reliability. Further information on reliability of
power devices is provided on www.ixys.com
.
RELIABILITY TESTS
High Temperature Reverse Bias (HTRB)
Failure Modes: Gradual degradation of break-down
characteristics due to presence of foreign materials
and polar/ionic contaminants disturbing the electric
field termination structure.
Sensitive Parameters:
BV
DSS
, BV
CES
, V
DRRM
, V
RRM
,
I
DSS
, I
CES
, I
DRM
, I
RRM
, V
TH
.
High Temperature Gate Bias (HTGB)
Failure Modes: Rupture of the gate oxide due to
localized thickness variations, structural anomalies,
particulates in the oxide, channel inversion due to
presence of mobile ions in the gate oxide.
Sensitive Parameters:
I
GSS
, I
GES
,V
TH
, I
DSS
, I
CES
.
Temperature Cycle
Failure modes: Thermal fatigue of silicon-metal and
metal-metal interfaces due to heating and cooling,
causing thermal and electrical performance degradation.
Sensitive Parameters:
R
thJC
, R
DS(on)
, V
CE(sat)
, V
T
, V
F
.
Humidity Test
Failure Modes: Degradation of electrical leakage
characteristics due to moisture penetration into plastic
packages.
Sensitive Parameters:
BV
DSS
, BV
CES
, V
DRRM
, V
RRM
,
I
DSS
, I
CES
, I
DRM
, I
RRM
, I
GSS
, I
GES
,
V
TH
.
Power Cycle
Failure Modes: Thermal fatigue of silicon-metal and
metal-metal interfaces due to heating and cooling can
cause thermal and electrical performance
degradation.
Sensitive Parameters:
R
thJC
, R
DS(on)
, V
CE(sat)
, V
T
, V
F,
I
DSS
,
I
CES
, I
DRM
, I
RRM
, BV
DSS
, BV
CES
, V
DRRM
,
V
RRM
.
TERMS IN TABLES
SUMMARY TABLES 1 AND 2:
AF: acceleration factor
AF = exp { Ea *[ (T
2
-T
1
) / ( T
2
* T
1
) ] / k } (1)
Ea: activation energy; @ HTRB Ea = 1.0 eV
@ HTGB Ea = 0.4 eV
k: Boltzmann’s constant 8.6·10
-5
eV/K
T
1
: abs. application junction temperature (273+Tj) K
T
2
: abs. test junction temperature (273+Tj) K
UCL: upper confidence limit (60%)
Total Failures @ 60% UCL:
N = r + dr (2)
r: number of failed devices
dr: additional term, depending on both r and UCL
MTTF: Mean Time To Failures
= 1/Failure Rate
FIT:
1 FIT = 1 failure / 10
9
hrs
TABLES 3:
ΔT: max Tj - min Tj during Test
DEFINITION OF FAILURE
Failure criteria are defined according to IEC 60747
standard series
