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NLV74HC238ADTR2G

P1-P3P4-P6P7-P8
MC74HC238A
www.onsemi.com
4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbo
l
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
−55°C to 25°C v 85°C v 125°C
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ± 0.1 ± 1.0 ± 1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4 40 160
mA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbo
l
Parameter
V
CC
V
Guaranteed Limit
Unit
−55°C to 25°C v 85°C v 125°C
t
PLH
,
t
PHL
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 6)
2.0
3.0
4.5
6.0
135
90
27
23
170
125
34
29
205
165
41
35
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, CS1 to Output Y
(Figures 4 and 6)
2.0
3.0
4.5
6.0
110
85
22
19
140
100
28
24
165
125
33
28
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, CS2 or CS3 to Output Y
(Figures 5 and 6)
2.0
3.0
4.5
6.0
120
90
24
20
150
120
30
26
180
150
36
31
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 4 and 6)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
C
in
Maximum Input Capacitance − 10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, V
CC
= 5.0 V
pF
55
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.
MC74HC238A
www.onsemi.com
5
Figure 3.
50%
t
PHL
t
PLH
V
CC
GND
Figure 4.
VALID VALID
OUTPUT Y 50%
t
f
t
r
V
CC
GND
t
PLH
t
TLH
90%
50%
10%
OUTPUT Y
INPUT CS1
t
PHL
90%
50%
10%
t
THL
INPUT A
SWITCHING WAVEFORMS
t
THL
t
TLH
V
CC
GND
t
r
t
PHL
t
PLH
OUTPUT Y
INPUT
CS2, CS3
90%
50%
10%
90%
50%
10%
Figure 5.
t
f
*Includes all probe and jig capacitance
Figure 6. Test Circuit
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active−low.
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic low.
OUTPUTS
Y0 − Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Active−high Decoded outputs. These outputs assume a
high level when addressed and the chip is selected. These
outputs remain low when not addressed or the chip is not
selected.
MC74HC238A
www.onsemi.com
6
A0
A1
A2
CS3
CS2
CS1
1
2
3
4
5
6
15
14
13
12
11
10
9
7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
EXPANDED LOGIC DIAGRAM
Figure 7. Logic Diagram
P1-P3P4-P6P7-P8

NLV74HC238ADTR2G

Mfr. #:
Buy NLV74HC238ADTR2G
Manufacturer:
ON Semiconductor
Description:
Encoders, Decoders, Multiplexers & Demultiplexers 1-of-8 Decoder/Demux
Lifecycle:
New from this manufacturer.
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