SIP32413DNP-T1-GE4

www.vishay.com
10
Document Number: 71437
S11-2472-Rev. B, 19-Dec-11
Vishay Siliconix
SiP32413, SiP32414, SiP32416
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
BLOCK DIAGRAM
PCB LAYOUT
Figure 34 - SiP32416 Switching
(V
IN
= 5 V, R
L
= 10 )
V
CNTRL
(2 V/div.)
R
L
= 10 Ω
C
L
= 0.1 µF
V
OUT
(2 V/div.)
I
OUT
(200 mA/div.)
Time (2 ms/div.)
Figure 35 - SiP32416 Turn-Off
(V
IN
= 5 V, R
L
= 10 )
V
CNTRL
(2 V/div.)
R
L
= 10 Ω
C
L
= 0.1 µF
V
OUT
(2 V/div.)
I
OUT
(200 mA/div.)
Time (1 µs/div.)
Figure 36 - Functional Block Diagram
+
-
-
+
IN1
CNTRL1
CNTRL2
IN2
OUT1
GND
OUT2
SiP32414 and SiP32416
only
Reverse
Blocking
Reverse
Blocking
Charge
Pump
Charge
Pump
Logic
Control
Logic
Control
Turn On
Slew Rate
Control
Turn On
Slew Rate
Control
Top Bottom
Figure 37 - PCB Layout for TDFN8 2 mm x 2 mm (type: FR4, size: 1.2" x 1.3", thickness: 0.062", copper thickness: 2 oz.)
SiP32413, SiP32414, SiP32416
Vishay Siliconix
Document Number: 71437
S11-2472-Rev. B, 19-Dec-11
www.vishay.com
11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DETAILED DESCRIPTION
SiP32413, SiP32414 and SiP32416 are dual n-channel
power MOSFETs designed as high side load switch with
slew rate control to prevent in-rush current. Once enable the
device charges the gate of the power MOSFET to 5 V gate
to source voltage while controlling the slew rate of the turn on
time. The mostly constant gate to source voltage keeps the
on resistance low through out the input voltage range. For
SiP32414, when disable the output discharge circuit turns on
to help pull the output voltage to ground more quickly. For all
parts, in disable mode, the reverse blocking circuit is
activated to prevent current from going back to the input in
case the output voltage is higher than the input voltage. Input
voltage is needed for the reverse blocking circuit to work
properly, it can be as low as V
IN(min.)
.
APPLICATION INFORMATION
Input Capacitor
While bypass capacitors on the inputs are not required,
2.2 µF or larger capacitors for C
IN
is recommended in almost
all applications. The bypass capacitors should be placed as
physically close as possible to the device’s input to be
effective in minimizing transients on the input. Ceramic
capacitors are recommended over tantalum because of their
ability to withstand input current surges from low impedance
sources such as batteries in portable devices.
Output Capacitor
A 0.1 µF capacitor or larger across V
OUT
and GND is
recommended to insure proper slew operation. C
OUT
may be
increased without limit to accommodate any load transient
condition with only minimal affect on the turn on slew rate
time. There are no ESR or capacitor type requirement.
Control
The CNTRL pins are compatible with both TTL and CMOS
logic voltage levels.
Protection Against Reverse Voltage Condition
SiP32413, SiP32414 and SiP32416 contain reverse blocking
circuitries to protect the current from going to the input from
the output in case where the output voltage is higher than the
input voltage when the main switch is off. Supply voltages as
low as the minimum required input voltage are necessary for
these circuitries to work properly.
Thermal Considerations
All three parts are designed to maintain constant output load
current. Due to physical limitations of the layout and
assembly of the device the maximum switch current is 2.4 A,
as stated in the Absolute Maximum Ratings table. However,
another limiting characteristic for the safe operating load
current is the thermal power dissipation of the package. To
obtain the highest power dissipation (and a thermal
resistance of 95) the power pad of the device should be
connected to a heat sink on the printed circuit board.
The maximum power dissipation in any application is
dependant on the maximum junction temperature,
T
J(max.)
= 125 °C, the junction-to-ambient thermal resistance
for the TDFN4 1.2 mm x 1.6 mm package,
J-A
= 95 °C/W,
and the ambient temperature, T
A
, which may be formulaically
expressed as:
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to about
580 mW.
So long as the load current is below the 2.4 A limit, the
maximum continuous switch current becomes a function two
things: the package power dissipation and the R
DS(ON)
at the
ambient temperature.
As an example let us calculate the worst case maximum load
current at T
A
= 70 °C. The worst case R
DS(ON)
at 25 °C
occurs at an input voltage of 1.2 V and is equal to 75 m. The
R
DS(ON
) at 70 °C can be extrapolated from this data using
the following formula:
R
DS(ON)
(at 70 °C) = R
DS(ON)
(at 25 °C) x (1 + T
C
x T)
Where T
C
is 3400 ppm/°C. Continuing with the calculation
we have
R
DS(ON)
(at 70 °C) = 75 m x (1 + 0.0034 x (70 °C - 25 °C))
= 86.5 m
The maximum current limit is then determined by
which in case is 2.6 A, assuming one switch turn on at a time.
Under the stated input voltage condition, if the 2.6 A current
limit is exceeded the internal die temperature will rise and
eventually, possibly damage the device.
To avoid possible permanent damage to the device and keep
a reasonable design margin, it is recommended to operate
the device maximum up to 2.4 A only as listed in the Absolute
Maximum Ratings table.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71437
.
95
125
(max.)
(max.)
A
A
J
A
J
T
TT
P
-
=
-
=
-
θ
) (
(max.)
(max.)
ON DS
LOAD
R
P
I <
Document Number: 67493 www.vishay.com
Revison: 07-Feb-11
1
Package Information
Vishay Siliconix
CASE OUTLINE FOR TDFN8 2 x 2
Note
1. All dimensions are in millimeters which will govern.
2. Max. package warpage is 0.05 mm.
3. Max. allowable burrs is 0.076 mm in all directions.
4. Pin #1 ID on top will be laser/ink marked.
5. Dimension applies to meatlized terminal and is measured
between 0.20 mm and 0.25 mm from terminal tip.
6. Applied only for terminals.
7. Applied for exposed pad and terminals.
Top View
Side View
Bottom View
K
K
L
D2
Pin 1 Indicator
(Optional)
8
7
6
5
1
2
3
4
b
5
e
E2
1
2
3
4
8
7
6
5
D
E
A
A3
A1
7
6
0.05 C
Index Area
(D/2 x E/2)
MILLIMETERS INCHES
DIM. MIN. NOM. MAX. MIN. NOM. MAX.
A 0.50 0.55 0.60 0.020 0.022 0.024
A1 0.00 - 0.05 0.000 - 0.002
A3 0.152 REF 0.006 REF
b 0.18 0.23 0.28 0.007 0.009 0.011
D 1.95 2.00 2.05 0.077 0.079 0.081
D2 0.75 0.80 0.85 0.030 0.031 0.033
e 0.50 BSC 0.020 BSC
E 1.95 2.00 2.05 0.077 0.079 0.081
E2 1.40 1.45 1.50 0.055 0.057 0.059
K - 0.20 - - 0.008 -
L 0.30 0.35 0.40 0.012 0.014 0.016
ECN: C11-0033 Rev. A, 07-Feb-11
DWG: 5997

SIP32413DNP-T1-GE4

Mfr. #:
Manufacturer:
Vishay / Siliconix
Description:
Power Switch ICs - Power Distribution 2A Dual Slew Rate Ctrl Load Switch
Lifecycle:
New from this manufacturer.
Delivery:
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