74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 5 of 19
NXP Semiconductors
74LVC373A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = High-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of P
tot
derates linearly with 4.5 mW/K.
Table 3. Functional table
[1]
Operating modes Input Internal latch Output
OE LE Dn Qn
Enable and read register
(transparent mode)
LHLLL
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable
outputs
HL l L Z
HL hHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +6.5 V
I
IK
input clamping current V
I
< 0 50 - mA
V
I
input voltage
[1]
0.5 +6.5 V
I
OK
output clamping current V
O
> V
CC
or V
O
< 0 - 50 mA
V
O
output voltage HIGH or LOW-state
[2]
0.5 V
CC
+ 0.5 V
3-state
[2]
0.5 +6.5 V
I
O
output current V
O
= 0 V to V
CC
- 50 mA
I
CC
supply current - 100 mA
I
GND
ground current 100 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[3]
-500 mW
