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ZL1505ALNFT1

P1-P3P4-P6P7-P9P10-P12P13-P13
ZL1505
10
FN6845.3
February 25, 2011
ZL1505 Overview
Theory of Operation
The ZL1505 is a synchronous N-channel MOSFET driver that is
intended for use with Zilker Labs Digital-DC PWM controllers to
enable a high-efficiency DC/DC conversion scheme. The
patented Digital-DC control scheme utilizes a closed-loop
algorithm to optimize the dead-time applied between the gate
drive signals for the high-side and low-side MOSFETs. By
monitoring the duty cycle of the resulting DC/DC converter
circuit, this dynamic routine continuously varies the MOSFET
dead times to optimize conversion efficiency in response to
varying circuit conditions. The ZL1505’s dual PWM input
configuration enables this optimization scheme to be applied
while minimizing the complexity within the driver device. Please
refer to the ZL2004
data sheet for details on the dynamic
dead-time optimization routine.
The ZL1505 integrates two powerful gate drivers that have been
optimized for step-down DC/DC conversion circuit configurations
whose output current can exceed 40A per phase. The ZL1505
also integrates a 30V bootstrap Schottky diode to minimize the
external components and provide a high drive voltage to the
high-side driver device.
Variable Gate Drive Current
The ZL1505 incorporates an innovative variable drive current
scheme that enables the user to optimize the gate drive current
levels to the requirements of the external MOSFETs used over a
wide range of operating frequencies. Each of the gate drivers
incorporates a logic input (HSEL and LSEL) that allows the user to
select the gate drive strength to 50% or 100% of the total rated
drive current.
With the HSEL pin connected to the BST pin, the high-side driver
can deliver the full rated gate drive current; with the HSEL pin
connected to the SW pin, the output current will be limited to
50% of the full rated output capability. With the LSEL pin
connected to VDD, the low-side driver can deliver the full rated
gate drive current; with the LSEL pin connected to GND, the
FIGURE 22. HIGH-SIDE DRIVER RISE TIME, t
RH
(CGH = 3nF,
T
A
= +25°C)
FIGURE 23. t
RH
WITH TEMPERATURE (C
GH
= 3nF, HSEL = BST)
FIGURE 24. HIGH-SIDE DRIVER FALL TIME, t
FH
(CGH = 3nF,
T
A
= +25°C)
FIGURE 25. t
FH
WITH TEMPERATURE (C
GH
= 3nF, HSEL = BST)
Typical Performance Curves Performance curves with temperature are measured at ambient temperatures (T
A
) of
+85°C, +25°C, and -25°C.
(Continued)
V
DD
(V)
4.5 7.57.06.56.05.55.0
17.5
11.5
13.5
15.5
5.5
9.5
7.5
3.5
t
RISE
(ns)
HSEL = SW
HSEL = BST
4.5 7.57.06.56.05.55.0
V
DD
(V)
8.5
5.5
6.5
7.5
3.5
4.5
t
RISE
(ns)
-25°C
+25°C
+85°C
4.5 7.57.06.56.05.55.0
V
DD
(V)
11.5
5.5
7.5
9.5
3.5
t
FALL
(ns)
HSEL = SW
HSEL = BST
4.5 7.57.06.56.05.55.0
V
DD
(V)
7.5
4.5
5.5
6.5
3.5
t
FALL
(ns)
-25°C
+25°C
+85°C
ZL1505
11
FN6845.3
February 25, 2011
output current will be limited to 50% of the full rated output
capability. Using HSEL and LSEL, the ZL1505 can be used across
a wide range of applications using only a simple PCB layout
change.
Also, the VDD pin is the gate drive bias supply for the external
MOSFETs. VDD can be used to vary the gate drive strength as
shown for the low-side driver in Figures 9 through 12 and for the
high-side driver in Figures 17 through 20.
Overlap Protection Circuit
The ZL1505 includes an internal watchdog circuit that prevents
excessive shoot-through current from occurring in the unlikely
event that the PWM converter places both switches in the ON
position. If the overlap time between the PWMH and PWML
pulses exceeds 30ns, the PWMH signal will be forced to the LOW
state until the overlap condition ceases, allowing normal
switching operation to continue.
Start-up Requirements
During power-up, the ZL1505 maintains both GH and GL outputs
in the LOW state while the V
IN
voltage is ramping up. Once the
V
DD
supply is within specification, the GH and GL pins may be
operated using the PWMH and PWML logic inputs respectively.
In the case where the PWM controller is powered from a supply
other than the ZL1505’s V
DD
supply, and the PWM controller is
powered up first, the PWM controller gate outputs should be kept
in low or in high-impedance state until the V
DD
supply is within
specification. Additionally, if the ZL1505 begins its power-down
sequence prior to the PWM controller then the PWM controller
gate outputs should be set in low or in high-impedance state
before the V
DD
voltage supply drops below its specified range.
Thermal Protection
When the junction temperature exceeds +150°C the high-side
driver output GH is forced to logic low state. The driver output is
allowed to switch logic states again once the junction
temperature drops below +134°C.
ZL1505
12
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6845.3
February 25, 2011
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products
for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ZL1505
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE REVISION CHANGE
2/15/11 FN6845.3 Added ZL1505ALNFT, ZL1505ALNFT1 and ZL1505ALNFT6 to “Ordering Information” on page 3. Added applicable lead finish
note (note 6).
2/9/11 Pg. 4: under “Absolute Maximum Ratings,” changed maximum voltage from 8V to 6V for the following pins:
From: “Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . -0.3V to 8V”
To: “Logic I/O Voltage for PWMH, PWML, LSEL Pins . . . -0.3V to 6V”
10/19/10 FN6845.2 “PWM Input Logic Low, VIL” on page 4, changed Max spec from 2.2V to 1.7V for “VDD = 6.5V”. Removed Min/Typ specs of 1.7/2
“PWM Input Logic Low, VIL” on page 4, changed Max spec from 1.9V to 1.4V for “VDD = 5.0V”. Removed Min/Typ specs of
1.5/1.7
“PWM Input Logic High, VIH” on page 4, changed Min spec from 2.8V to 3.4V for “VDD = 6.5V”. Removed Typ/Max specs of
3.1/3.4
“PWM Input Logic High, VIH” on page 4, changed Min spec from 2.2V to 2.7V for “VDD = 5.0V”. Removed Typ/Max specs of
2.5/2.7
7/9/10 On page 4, Electrical Specifications Table, the parameter “Minimum GH On-time Pulse, tGH,ON (Note 12)”, removed 14 and 20
from Max column. In TYP column, changed 10 to 14 and 14 to 20.
On page 4, Electrical Specifications Table, the parameter “Minimum PWMH On-time to Produce GH Pulse, tPWMH,ON (Note
11)”, removed 12 from Max column. In TYP column, changed 8.5 to 12.
On page 4, Electrical Specifications Table, the parameter “Minimum PWMH Off-time to Produce Valid GH Pulse, tPWMH,OFF”,
removed 17 from Max column. In TYP column, changed 13 to 17.
Replaced POD drawing with updated revisions and changes were as follows:
Converted to new standards by adding land pattern and moving dimensions from table onto drawing
2/14/09 FN6845.1 Assigned file number FN6845 to datasheet as this will be the first release with an Intersil file number. Replaced header and
footer with Intersil header and footer. Updated disclaimer information to read “Intersil and it’s subsidiaries including Zilker Labs,
Inc.” No changes to datasheet content
12/4/09 FN6845.0 Converted to new Intersil template. Changed in Abs Max Ratings “Low-Side Drive Voltage for GL pin” from “(GND - 0.3) to (VIN +
0.3)” to “(GND - 0.3) to (VDD + 0.3)”. Removed Bullet "Adjustable gate drive voltage: 4.5V to 7.5V" and "Exposed pad 3mmx3mm
DFN-10 Package" from Features. Intersil Standards applied are: Added Related Information, Updated ordering information with
Notes that includes MSL. Updated Abs Max Ratings with notes, added ESD Ratings and Latchup, added Boldface text in
Electrical Spec Table. Added POD
P1-P3P4-P6P7-P9P10-P12P13-P13

ZL1505ALNFT1

Mfr. #:
Buy ZL1505ALNFT1
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers SYNC MSFT DRVR TR1K
Lifecycle:
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