Data Sheet OP177
Rev. H | Page 3 of 16
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
At V
S
= ±15 V, T
A
= 25°C, unless otherwise noted.
Table 1.
OP177F OP177G
Symbol
Test Conditions/Comments
Min
Typ
Max
Min
Typ
Max
Unit
V
OS
10
25
20
60
μV
LONG-TERM INPUT OFFSET
1
Voltage Stability ΔV
OS
/time 0.3 0.4 μV/mo
INPUT OFFSET CURRENT I
OS
0.3 1.5 0.3 2.8 nA
I
B
−0.2
+1.2
+2
−0.2
+1.2
+2.8
nA
INPUT NOISE VOLTAGE e
n
f
O
= 1 Hz to 100 Hz
2
118 150 118 150 nV rms
INPUT NOISE CURRENT i
n
f
O
= 1 Hz to 100 Hz
2
3 8 3 8 pA rms
INPUT RESISTANCE
Differential Mode
3
R
IN
26 45 18.5 45 MΩ
R
INCM
200
200
GΩ
INPUT VOLTAGE RANGE
4
IVR ±13 ±14 ±13 ±14 V
COMMON-MODE REJECTION RATIO CMRR V
CM
= ±13 V 130 140 115 140 dB
POWER SUPPLY REJECTION RATIO PSRR V
S
= ±3 V to ±18 V 115 125 110 120 dB
LARGE SIGNAL VOLTAGE GAIN A
VO
R
L
≥ 2 kΩ, V
O
= ±10 V
5
5000 12,000 2000 6000 V/mV
OUTPUT VOLTAGE SWING V
O
R
L
≥ 10 kΩ ±13.5 ±14.0 ±13.5 ±14.0 V
R
L
≥ 2 kΩ ±12.5 ±13.0 ±12.5 ±13.0 V
R
L
≥ 1 kΩ ±12.0 ±12.5 ±12.0 ±12.5 V
SLEW RATE
2
SR R
L
≥ 2 kΩ 0.1 0.3 0.1 0.3 V/μs
CLOSED-LOOP BANDWIDTH
2
BW A
VCL
= 1 0.4 0.6 0.4 0.6 MHz
OPEN-LOOP OUTPUT RESISTANCE R
O
60 60
POWER CONSUMPTION P
D
V
S
= ±15 V, no load 50 60 50 60 mW
V
S
= ±3 V, no load 3.5 4.5 3.5 4.5 mW
SUPPLY CURRENT I
SY
V
S
= ±15 V, no load 1.6 2 1.6 2 mA
OFFSET ADJUSTMENT RANGE R
P
= 20 kΩ ±3 ±3 mV
1
Long-term input offset voltage stability refers to the averaged trend line of V
OS
vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in V
OS
during the first 30 operating days are typically less than 2.0 μV.
2
Sample tested.
3
Guaranteed by design.
4
Guaranteed by CMRR test condition.
5
To ensure high open-loop gain throughout the ±10 V output range, A
VO
is tested at −10 V V
O
0 V, 0 V ≤ V
O
+10 V, and 10 V ≤ V
O
+10 V.
OP177 Data Sheet
Rev. H | Page 4 of 16
At V
S
= ±15 V, −40°C ≤ T
A
≤ +85°C, unless otherwise noted.
Table 2.
OP177F OP177G
Parameter Symbol Test Conditions/Comments Min Typ Max Min Typ Max Unit
INPUT
Input Offset Voltage V
OS
15 40 20 100 μV
Average Input Offset Voltage Drift
1
TCV
OS
0.1 0.3 0.7 1.2 μV/°C
Input Offset Current I
OS
0.5 2.2 0.5 4.5 nA
Average Input Offset Current Drift
2
TCI
OS
1.5 40 1.5 85 pA/°C
Input Bias Current I
B
−0.2 +2.4 +4 +2.4 ±6 nA
Average Input Bias Current Drift
2
TCI
B
8 40 15 60 pA/°C
Input Voltage Range
3
IVR ±13 ±13.5 ±13 ±13.5 V
COMMON-MODE REJECTION RATIO CMRR V
CM
= ±13 V 120 140 110 140 dB
POWER SUPPLY REJECTION RATIO PSRR V
S
= ±3 V to ±18 V 110 120 106 115 dB
LARGE-SIGNAL VOLTAGE GAIN
4
A
VO
R
L
≥ 2 kΩ, V
O
= ±10 V 2000 6000 1000 4000 V/mV
OUTPUT VOLTAGE SWING V
O
R
L
≥ 2 kΩ ±12 ±13 ±12 ±13 V
POWER CONSUMPTION P
D
V
S
= ±15 V, no load 60 75 60 75 mW
SUPPLY CURRENT I
SY
V
S
= ±15 V, no load 20 2.5 2 2.5 mA
1
TCV
OS
is sample tested.
2
Guaranteed by endpoint limits.
3
Guaranteed by CMRR test condition.
4
To ensure high open-loop gain throughout the ±10 V output range, A
VO
is tested at −10 V ≤ V
O
≤ 0 V, 0 V ≤ V
O
≤ +10 V, and −10 V ≤ V
O
≤ +10 V.
TEST CIRCUITS
200k
50
V
OS
=
V
O
4000
V
O
00289-003
OP177
+
Figure 3. Typical Offset Voltage Test Circuit
OP177
V+
OUTPUT
+
+
INPUT
V–
20k
V
OS
TRIM RANGE IS
TYPICALLY ±3.0mV
00289-004
Figure 4. Optional Offset Nulling Circuit
OP177
+
PINOUTS SHOWN FOR
P AND Z PACKAGES
0
0289-005
+20V
–20V
20k
Figure 5. Burn-In Circuit
Data Sheet OP177
Rev. H | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Ratings
Supply Voltage ±22 V
Internal Power Dissipation
1
500 mW
Differential Input Voltage ±30 V
Input Voltage ±22 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 60 sec) 300°C
DICE Junction Temperature (T
J
) −65°C to +150°C
1
For supply voltages less than ±22 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θ
JA
is specified for worst-case mounting conditions, that is, θ
JA
is
specified for device in socket for PDIP; θ
JA
is specified for
device soldered to printed circuit board for SOIC package.
Table 4. Thermal Resistance
Package Type
θ
JA
θ
JC
Unit
8-Lead PDIP (P-Suffix) 103 43 °C/W
8-Lead SOIC (S-Suffix)
158
43
°C/W
ESD CAUTION

OP177GS-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers ULTRA-PREC IC Low Supply Crnt 2mA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union