Document Number: 38-05029 Rev. *C Page 6 of 12
Switching Characteristics
Over the Operating Range
[4]
Parameter Description
7C168A-20
Unit
Min. Max.
READ CYCLE
t
RC
Read cycle time 20 – ns
t
AA
Address to data valid – 20 ns
t
OHA
Output hold from address change 5 – ns
t
ACE
CE LOW to data valid – 20 ns
t
LZCE
CE LOW to low Z
[5]
5 – ns
t
HZCE
CE HIGH to high Z
[5, 6]
– 8 ns
t
PU
CE LOW to power-up 0 – ns
t
PD
CE HIGH to power-down – 20 ns
t
RCS
Read command set-up 0 – ns
t
RCH
Read command hold 0 – ns
WRITE CYCLE
[7]
t
WC
Write cycle time 20 – ns
t
SCE
CE LOW to write end 15 – ns
t
AW
Address set-up to write end 15 – ns
t
HA
Address hold from write end 0 – ns
t
SA
Address set-up to write start 0 – ns
t
PWE
WE pulse width 15 – ns
t
SD
Data set-up to write end 10 – ns
t
HD
Data hold from write end 0 – ns
t
LZWE
WE HIGH to low Z
[5]
7 – ns
t
HZWE
WE LOW to high Z
[5, 6]
5 – ns
Switching Waveforms
Notes
4. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
I
OL
/I
OH
and 30 pF load capacitance.
5. At any given temperature and voltage condition, t
HZ
is less than t
LZ
for all devices. Transition is measured 500 mV from steady state voltage with specified loading in part (b)
of AC Test Loads and Waveforms.
6. t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (a) of Test Loads and Waveforms. Transition is measured 500 mV from steady state voltage.
7. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can terminate a
write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
8. WE
is HIGH for read cycle.
9. Device is continuously selected, CE
= V
IL
.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
t
RC
t
AA
t
OHA
[8, 9]
C168A-5
Figure 2. Read Cycle No.1
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