XCR3128XL 128 Macrocell CPLD
4 www.xilinx.com DS016 (v2.6) March 31, 2006
Product Specification
R
T
ECSU
Register clock enable setup time 2.0 - 2.5 - 3.0 - ns
T
ECHO
Register clock enable hold time 3.0 - 4.5 - 5.5 - ns
T
COI
Register clock to output delay - 1.0 - 1.3 - 1.6 ns
T
AOI
Register async. S/R to output delay - 2.5 - 2.3 - 2.1 ns
T
RAI
Register async. recovery - 4.0 - 5.0 - 6.0 ns
T
PTCK
Product term clock delay - 2.5 - 2.7 - 3.3 ns
T
LOGI1
Internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns
T
LOGI2
Internal logic delay (PLA OR term) - 2.5 - 3.2 - 4.2 ns
Feedback Delays
T
F
ZIA delay - 1.2 - 2.9 - 3.5 ns
Time Adders
T
LOGI3
Fold-back NAND delay - 2.0 - 2.5 - 3.0 ns
T
UDA
Universal delay - 1.7 - 2.2 - 2.7 ns
T
SLEW
Slew rate limited delay - 4.0 - 5.0 - 6.0 ns
Notes:
1. These parameters guaranteed by design and/or characterization, not testing.
2. See the CoolRunner XPLA family data sheet (
DS012) for timing model.
Symbol Parameter
-6 -7 -10
UnitMin. Max. Min. Max. Min. Max.
