REVISION B 08/25/14 7 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
8343-01 DATA SHEET
Table 5C. AC Electrical Characteristics, V
DD
=V
DD2
= 3.3V ±5%, V
DD1
= 2.5V ±5%, T
A
= 0°C to 70°C
1
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 200 MHz
tsk(o) Output Skew
2
Measured on rising edge @ V
DDx
/2 250 ps
NOTE 1: All parameters measured at f
MAX
unless noted otherwise.
NOTE 2: Defined as skew across outputs at the same supply voltages within a bank, and with equal load conditions.
Table 5D. AC Electrical Characteristics, V
DD
3.3V ±5%, V
DD1
=V
DD2
= 2.5V ±5%, T
A
= 0°C to 70°C
1
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 133 MHz
t
pLH
Propagation Delay
2
f 200MHz 2.0 4.0 ns
tsk(o) Output Skew
3, 4
Measured on rising edge @ V
DDx
/2 250 ps
tsk(pp) Part-to-Part Skew
4, 5
Measured on rising edge @ V
DDx
/2 1ns
t
R
/t
F
Output Rise/ Fall Time 20% to 80% 0.4 1.0 ns
odc Output Duty Cycle f 133MHz 40 60 %
NOTE 1: All parameters measured at f
MAX
unless noted otherwise.
NOTE 2: Measured from V
DD
/2 of the input to V
DDx
/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDx
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at V
DDx
/2.
8343-01 DATA SHEET
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER 8 REVISION B 08/25/14
Parameter Measurement Information
3.3V Core/3.3V Output Load Test Circuit
2.5V Core/2.5V Output Load Test Circuit
Part-to-Part Skew
Propagation Delay
3.3V Core/2.5V Output Load Test Circuit
Output Skew
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
SCOPE
Qx
GND
1.65V±5%
-1.65V±5%
V
DD,
V
DD1,
V
DD2
SCOPE
Qx
GND
V
DD,
1.25V±5%
-1.25V±5%
V
DD1,
V
DD2
tsk(pp)
V
DDx
2
V
DDx
2
Part 1
Part 2
Qx
Qy
t
PD
V
DDx
2
V
DDx
2
CLK
Q0:Q15
SCOPE
Qx
GND
V
DD
2.05V±5%
-1.25V±5%
V
DD1
,
1.25V±5%
V
DD2
tsk(o)
V
DDx
2
V
DDx
2
Qx
Qy
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDx
2
x 100%
t
PW
Q0:Q15
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
REVISION B 08/25/14 9 LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
8343-01 DATA SHEET
Reliability Information
Table 6.
JA
vs. Air Flow Table for a 32-Lead LQFP
1
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W
Transistor Count
The transistor count for 8343-01 is 985.
NOTE 1: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
JA
by Velocity

8343AY-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-16 LVCMOS/LVTTL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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