ADN4661
Rev. 0 | Page 4 of 12
AC CHARACTERISTICS
V
CC
= 3 V to 3.6 V; R
L
= 100 Ω; C
L
1
= 15 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
2
Symbol Min Typ Max Unit Conditions/Comments
3, 4
Differential Propagation Delay High to Low t
PHLD
0.3 0.8 1.5 ns See Figure 3 and Figure 4
Differential Propagation Delay Low to High t
PLHD
0.3 1.1 1.5 ns See Figure 3 and Figure 4
Differential Pulse Skew |t
PHLD
− t
PLHD
|
5
t
SKD1
0 0.3 0.7 ns See Figure 3 and Figure 4
Differential Part-to-Part Skew
6
t
SKD3
0 1.0 ns See Figure 3 and Figure 4
Differential Part-to-Part Skew
7
t
SKD4
0 1.2 Ns See Figure 3 and Figure 4
Rise Time t
TLH
0.2 0.5 1.0 ns See Figure 3 and Figure 4
Fall Time t
THL
0.2 0.5 1.0 ns See Figure 3 and Figure 4
Maximum Operating Frequency
8
f
MAX
350 MHz See Figure 3
1
C
L
includes probe and jig capacitance.
2
AC parameters are guaranteed by design and characterization.
3
Generator waveform for all tests, unless otherwise specified: f = 50 MHz, Z
O
= 50 Ω, t
TLH
≤ 1 ns, and t
THL
≤ 1 ns.
4
All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5
t
SKD1
= |t
PHLD
− t
PLHD
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6
t
SKD3
, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same V
CC
and within 5°C of each other within the operating temperature range.
7
t
SKD4
, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperatures and voltage ranges, and across process distribution. t
SKD4
is defined as |maximum − minimum| differential propagation delay.
8
f
MAX
generator input conditions: t
TLH
= t
THL
< 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, V
OD
> 250 mV, all channels
switching.
Test Circuits and Timing Diagrams
07876-002
R
L
/2
R
L
/2
D
IN
D
OUT+
D
OUT–
CC
V
CC
V
OS
V
OD
VV
Figure 2. Test Circuit for Driver V
OD
and V
OS
07876-003
C
L
C
L
D
IN
D
OUT+
D
OUT–
NOTES
1. C
L
INCLUDES PROBE AND JIG CAPACITANCE.
SIGNAL
GENERATOR
CC
50Ω
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
07876-004
D
IN
V
DIFF
t
PLHD
t
PHLD
V
DIFF
= D
OUT+
–D
OUT–
V
OH
V
OL
V
OD
3
1.5V
0V (DIFFERENTIAL)
0V
80%
20%
0V
D
OUT+
D
OUT–
t
TLH
t
THL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
