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IDT85304-01PGG8

P1-P3P4-P6P7-P9P10-P11
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
FEBRUARY 2009
2006 Integrated Device Technology, Inc. DSC 6174/8c
IDT85304-01
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-3.3V
LVPECL FANOUT BUFFER
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Five differential 3.3V LVPECL outputs
• Selectable differential CLK, xCLK, or LVPECL clock inputs
• CLK, xCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, SSTL, and HCSL
• PCLK, xPCLK supports the following input types: LVPECL, CML,
and SSTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on xCLK input
• Output skew: 35ps (max.)
• Part-to-part skew: as low as 150ps
• Propagation delay: 2.1ns (max.)
• 3.3V operating supply
• Available in TSSOP package
DESCRIPTION:
The IDT85304-01 is a low skew, high performance 1-to-5 differential-to-
3.3V LVPECL clock generator-divider. It has two selectable clock inputs. The
CLK/ xCLK pair can accept most standard differential input levels. The PCLK/
xPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable
is internally synchronized to eliminate runt pulses on the outputs during
asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the IDT85304-
01 ideal for those applications that demand well-defined performance and
repeatability.
FUNCTIONAL BLOCK DIAGRAM
CLK_EN
CLK
xCLK
PCLK
xPCLK
CLK_SEL
0
1
D
LE
Q
Q0
xQ0
Q1
xQ1
Q2
xQ2
Q3
xQ3
Q4
xQ4
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol Description Max Unit
VDD Power Supply Voltage 4.6 V
VI Input Voltage –0.5 to VDD+0.5 V
VO Output Voltage –0.5 to VDD+0.5 V
θJA Package Thermal Impedance (0 lfpm) 92.6 °C/W
T
STG Storage Temperature –65 to +150 ° C
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description Typ. Max. Unit
CIN Input Capacitance — 4 pF
RPULLUP Input Pullup Resistor 51 — K Ω
RPULLDOWN Input Pulldown Resistor 51 — K Ω
TSSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
xQ0
Q1
xQ1
Q2
xQ2
Q3
xQ3
Q4
xQ4
V
DD
CLK_EN
V
DD
xPCLK
PCLK
V
EE
xCLK
CLK
CLK_SEL
V
DD
PIN DESCRIPTION
(1)
Symbol Number Type Description
xQ0, Q0 1, 2 Output Differential Output Pair. LVPECL interface levels.
xQ1, Q1 3, 4 Output Differential Output Pair. LVPECL interface levels.
xQ2, Q2 5, 6 Output Differential Output Pair. LVPECL interface levels.
xQ3, Q3 7, 8 Output Differential Output Pair. LVPECL interface levels.
xQ4, Q4 9, 10 Output Differential Output Pair. LVPECL interface levels.
VDD 11, 18, 20 Power Positive Supply Pins
CLK_SEL 12 Input Pulldown Clock Select Input. When HIGH, selects PCLK / xPCLK inputs. When LOW, selects
CLK / xCLK inputs. LVTTL / LVCMOS interface levels.
CLK 13 Input Pulldown Non-Inverting Differential Clock Input
xCLK 14 Input Pullup Inverting Differential Clock Input
VEE 15 Power Negative Supply Pin
PCLK 16 Input Pulldown Non-Inverting Differential LVPECL Clock Input
xPCLK 17 Input Pullup Inverting Differential LVPECL Clock Input
CLK_EN 19 Input Pullup Synchronizing Clock Enable. When HIGH, clock outputs follow clock input. When
LOW, Q outputs are forced LOW, xQ outputs are forced HIGH. LVTTL / LVCMOS
interface levels.
NOTE:
1. Pullup and Pulldown refer to internal input resistors. See Capacitance table for typical values.
3
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-3.3V LVPECL
CONTROL INPUT FUNCTION TABLE
(1,2)
Inputs Outputs
CLK_EN CLK_SEL Selected Source Q0:Q4 xQ0:xQ4
0 0 CLK, xCLK Disabled; LOW Disabled; HIGH
0 1 PCLK, xPCLK Disabled; LOW Disabled; HIGH
1 0 CLK, xCLK Enabled Enabled
1 1 PCLK, xPCLK Enabled Enabled
NOTES:
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below.
2. In active mode, the state of the outputs is a function of the CLK / xCLK and PCLK / xPCLK inputs as described in the Clock Input Function table.
CLOCK INPUT FUNCTION TABLE
(1)
Inputs Outputs
CLK or PCLK xCLK or xPCLK Q0:Q4 xQ0:xQ4 Input to Output Mode Polarity
0 1 L H Differential to Differential Non-Inverting
1 0 H L Differential to Differential Non-Inverting
0 Biased
(2)
L H Single-Ended to Differential Non-Inverting
1 Biased
(2)
H L Single-Ended to Differential Non-Inverting
Biased
(2)
0 H L Single-Ended to Differential Inverting
Biased
(2)
1 L H Single-Ended to Differential Inverting
NOTES:
1. H = HIGH
L = LOW
2. See Single-Ended Signal diagram under Application Information at the end of this datasheet.
CLK_EN
xCLK, xPCLK
xQ0, xQ1, xQ2, xQ3, xQ4
≈
≈
Disabled
Enabled
≈
Q0, Q1, Q2, Q3, Q4
CLK, PCLK
CLK_EN Timing Diagram
P1-P3P4-P6P7-P9P10-P11

IDT85304-01PGG8

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Manufacturer:
Description:
IC CLK BUFFER 1:5 650MHZ 20TSSOP
Lifecycle:
New from this manufacturer.
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