ISL6614BCRZ Datasheet ISL6614BIBZ-T, ISL6614BCBZ, ISL6614BCRZ-T | P7-P9

FN9206.3

May 5, 2008

Description

Operation

Designed for versatility and speed, the ISL6614B MOSFET

driver controls both high-side and low-side N-Channel FETs of

two half-bridge power trains from two externally provided PWM

signals.

Prior to VCC exceeding its POR level, the Pre-POR

overvoltage protection function is activated during initial start-

up; the upper gate (UGATE) is held low and the lower gate

(LGATE), controlled by the Pre-POR overvoltage protection

circuits, is connected to the PHASE. Once the VCC voltage

surpasses the VCC Rising Threshold (See the “Electrical

Specifications” table on page 5), the PWM signal takes control

of gate transitions. A rising edge on PWM initiates the turn-off of

the lower MOSFET (see “TIMING DIAGRAM” on page 7). After

a short propagation delay [t

PDLL

], the lower gate begins to fall.

Typical fall times [t

] are provided in the “Electrical

Specifications” table on page 5. Adaptive shoot-through

circuitry monitors the PHASE voltage and determines the upper

gate delay time [t

PDHU

]. This prevents both the lower and

upper MOSFETs from conducting simultaneously. Once this

delay period is complete, the upper gate drive begins to rise

] and the upper MOSFET turns on.

A falling transition on PWM results in the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [t

PDLU

] is encountered before the upper

gate begins to fall [t

]. Again, the adaptive shoot-through

circuitry determines the lower gate delay time, t

PDHL

. The

PHASE voltage and the UGATE voltage are monitored, and

the lower gate is allowed to rise after PHASE drops below a

level or the voltage of UGATE to PHASE reaches a level

depending upon the current direction (See the following

section for details). The lower gate then rises [t

], turning on

the lower MOSFET.

Advanced Adaptive Zero Shoot-Through Deadtime

Control (Patent Pending)

These drivers incorporate a unique adaptive deadtime control

technique to minimize deadtime, resulting in high efficiency

from the reduced freewheeling time of the lower MOSFETs’

body-diode conduction, and to prevent the upper and lower

MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.2V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

to rise. An auto-zero comparator is used to correct the r

DS(ON)

drop in the phase voltage preventing from false detection of the

-0.2V phase level during r

DS(ON)

conduction period. In the

case of zero current, the UGATE is released after 35ns delay of

the LGATE dropping below 0.5V. During the phase detection,

the disturbance of LGATE’s falling transition on the PHASE

node is blanked out to prevent falsely tripping. Once the

PHASE is high, the advanced adaptive shoot-through circuitry

monitors the PHASE and UGATE voltages during a PWM

falling edge and the subsequent UGATE turn-off. If either the

UGATE falls to less than 1.75V above the PHASE or the

PHASE falls to less than +0.8V, the LGATE is released to

turn-on.

Three-State PWM Input

A unique feature of these drivers and other Intersil drivers is

the addition of a shutdown window to the PWM input. If the

PWM signal enters and remains within the shutdown window

for a set holdoff time, the driver outputs are disabled and

both MOSFET gates are pulled and held low. The shutdown

state is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the the “Electrical Specifications” table

PWM

UGATE

LGATE

PDHU

PDLL

TSSHD

PDTS

1.5V<PWM<3.2V

1.0V<PWM<2.6V

PDLU

PDHL

TSSHD

FIGURE 1. TIMING DIAGRAM

ISL6614B

FN9206.3

May 5, 2008

on page 5 determine when the lower and upper gates are

enabled.

This feature helps prevent a negative transient on the output

voltage when the output is shut down, eliminating the

Schottky diode that is used in some systems for protecting

the load from reversed output voltage events.

In addition, more than 400mV hysteresis also incorporates

into the three-state shutdown window to eliminate PWM

input oscillations due to the capacitive load seen by the

PWM input through the body diode of the controller’s PWM

output when the power-up and/or power-down sequence of

bias supplies of the driver and PWM controller are required.

Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored.

Once the rising VCC voltage exceeds 6.9V (typically),

operation of the driver is enabled and the PWM input signal

takes control of the gate drives. If VCC drops below the

falling threshold of 5.6V (typically), operation of the driver is

disabled.

Pre-POR Overvoltage Protection

Prior to VCC exceeding its POR level, the upper gate is held

low and the lower gate is controlled by the overvoltage

protection circuits during initial startup. The PHASE is

connected to the gate of the low side MOSFET (LGATE),

which provides some protection to the microprocessor if the

upper MOSFET(s) is shorted during initial start-up. For

complete protection, the low side MOSFET should have a

gate threshold well below the maximum voltage rating of the

load/microprocessor.

When VCC drops below its POR level, both gates pull low

and the Pre-POR overvoltage protection circuits are not

activated until VCC resets.

Internal Bootstrap Device

Both drivers feature an internal bootstrap schottky diode.

Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor

from overcharging due to the large negative swing at the

trailing-edge of the PHASE node. This reduces voltage

stress on the boot to phase pins.

The bootstrap capacitor must have a maximum voltage

rating above UVCC + 5V and its capacitance value can be

chosen from Equation 1:

where Q

is the amount of gate charge per upper MOSFET

at V

GS1

gate-source voltage and N

is the number of

control MOSFETs per channel. The ΔV

BOOT_CAP

term is

defined as the allowable droop in the rail of the upper gate

drive.

As an example, suppose two IRLR7821 FETs are chosen as

the upper MOSFETs. The gate charge, Q

, from the data

sheet is 10nC at 4.5V (V

) gate-source voltage. Then the

GATE

is calculated to be 53nC for PVCC = 12V. We will

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.267µF is required.

Gate Drive Voltage Versatility

The ISL6614B provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The ISL6614B

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously. Connecting a SOT-23 package

type of dual Schottky diodes from the VCC to BOOT1 and

BOOT2 can bypass the internal bootstrap devices of both

upper gates so that the part can operate as a dual ISL6612B

driver, which has a fixed VCC (7V to 12V typically) on the

upper gate and a programmable lower gate drive voltage.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency (f

), the output drive impedance, the

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

+125°C. The maximum allowable IC power dissipation for

the SO14 package is approximately 1W at room

temperature, while the power dissipation capacity in the

BOOT_CAP

GATE

ΔV

BOOT_CAP

--------------------------------------

≥

GATE

PVCC•

GS1

------------------------------------

•=

(EQ. 1)

50nC

20nC

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

ΔV

BOOT_CAP

(V)

BOOT_CAP

(µF)

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.30.0 0.1 0.2 0.4 0.5 0.6 0.90.7 0.8 1.0

GATE

= 100nC

ISL6614B

FN9206.3

May 5, 2008

QFN packages, with an exposed heat escape pad, is around

2W. See “Layout Considerations” on page 9 for thermal

transfer improvement suggestions. When designing the

driver into an application, it is recommended that the

following calculation is used to ensure safe operation at the

desired frequency for the selected MOSFETs. The total gate

drive power losses due to the gate charge of MOSFETs and

the driver’s internal circuitry and their corresponding average

driver current can be estimated with Equations 2 and 3,

respectively,

where the gate charge (Q

and Q

) is defined at a

particular gate to source voltage (V

GS1

and V

GS2

) in the

corresponding MOSFET datasheet; I

is the driver’s total

quiescent current with no load at both drive outputs; N

and N

are number of upper and lower MOSFETs,

respectively; PVCC is the drive voltages for both upper and

lower FETs, respectively. The I

VCC product is the

quiescent power of the driver without capacitive load and is

typically 200mW at 300kHz.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

resistors (R

and R

) and the internal gate resistors

GI1

and R

GI2

) of MOSFETs. Figures 3 and 4 show the

typical upper and lower gate drives turn-on transition path.

The power dissipation on the driver can be roughly

estimated in Equation 4:

Layout Considerations

For heat spreading, place copper underneath the IC whether

it has an exposed pad or not. The copper area can be

extended beyond the bottom area of the IC and/or

connected to buried copper plane(s) with thermal vias. This

combination of vias for vertical heat escape, extended

copper plane, and buried planes for heat spreading allows

the IC to achieve its full thermal potential.

Place each channel power component as close to each

other as possible to reduce PCB copper losses and PCB

parasitics: shortest distance between DRAINs of upper FETs

and SOURCEs of lower FETs; shortest distance between

DRAINs of lower FETs and the power ground. Thus, smaller

amplitudes of positive and negative ringing are on the

switching edges of the PHASE node. However, some space

in between the power components is required for good

airflow. The traces from the drivers to the FETs should be

kept short and wide to reduce the inductance of the traces

and to promote clean drive signals.

Qg_TOT

Qg_Q1

• 2P

Qg_Q2

• I

VCC•++=

(EQ. 2)

Qg_Q1

PVCC

•

GS1

---------------------------------------

• N

•=

Qg_Q2

PVCC

•

GS2

---------------------------------------

• N

•=

•

GS1

----------------------------- -

•

GS2

----------------------------- -

⎝⎠

⎜⎟

⎛⎞

2• I

+•=

(EQ. 3)

2P•

DR_UP

2P•

DR_LOW

VCC•++=

(EQ. 4)

DR_UP

HI1

EXT1

--------------------------------------

LO1

EXT1

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

Qg_Q1

---------------------

•=

DR_LOW

HI2

EXT2

--------------------------------------

LO2

EXT2

----------------------------------------

⎝⎠

⎜⎟

⎛⎞

Qg_Q2

---------------------

•=

EXT1

GI1

-------------

EXT2

GI2

-------------

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

GI1

BOOT

HI1

LO1

PHASE

PVCC

GI2

HI2

LO2

ISL6614B

P1-P3 P4-P6 P7-P9 P10-P11

ISL6614BCRZ

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Gate Drivers DL SYNCH BUCK MSFT HV DRVR LW POR 16LD

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