CS5371 CS5372
14 DS255F3
achieved. During this time, the MFLAG pin transi-
tions from low to high to signal an error condition.
The analog input signal must be reduced to within
the full-scale range for at least 32 MCLK cycles for
the modulator to recover from an unstable condi-
tion.
The MFLAG output connects to a dedicated input
on the digital filter, causing an error bit to be set in
the status portion of the digital output data word
when detected.
8. POWER MODES
Four power modes are available when using the
CS5371/72 modulators. Normal power and low
power modes are operational modes, power down
and micro-power modes are non-operational
standby modes.
8.1. Normal Power Mode
The normal operational mode for the modulators,
LPWR=0 and MCLK=2.048 MHz, provides the
best performance with power consumption of
25 mW per channel. This power mode is recom-
mended when maximum conversion accuracy is
required.
8.2. Low Power Mode - LPWR
The modulators have a low-power operational
mode, LPWR=1 and MCLK=1.024 MHz, that re-
duces power consumption to 15 mW per channel
at the expense of 3 dB of dynamic range. This op-
erational mode is recommended when minimizing
power is more important than maximizing dynamic
range.
When operated with LPWR=1, the modulator sam-
pling clock (MCLK / 4) must be restricted to rates
of 256 kHz or less, which requires MCLK to run at
1.024 MHz or less. Operating in low power mode
with modulator sample rates greater than 256 kHz
will significantly degrade total harmonic distortion
performance.
8.3. Power Down Mode - PWDN
The modulators have a power down mode,
PWDN=1 and MCLK=Active, that disables the op-
eration of the selected modulator channel and re-
duces its power consumption to 1 mW. Each
modulator has an independent power down pin,
PWDN on the CS5371 and PWDN1, PWDN2 on
the CS5372. Note that when the modulators are
powered down and MCLK is active, the internal
clock generator is still drawing minimal currents.
8.4. Micro-power Mode
Standby power consumption of the modulators can
be minimized by placing them into a micro-power
mode, PWDN=1 and MCLK=0. Micro-power mode
requires setting the PWDN pin and halting MCLK
to remove the clock generator input current. Micro-
power mode consumes only 10 µW of power.
9. POWER SUPPLY
The CS5371/72 modulators have one positive an-
alog power supply pin, VA+, one negative analog
power supply pin, VA-, one digital power supply
pin, VD, and one digital ground pin, DGND. The
analog and digital circuitry is separated internally
to enhance performance, therefore power must be
supplied to all three supply pins and the digital
ground pin must be connected to system ground.
9.1. Power Supply Configurations
The CS5371/72 analog supplies can be powered
by a single +5 V supply and analog ground, or by
dual supplies of ± 2.5 V. When using dual sup-
plies, the positive and negative analog power sup-
plies must satisfy the following conditions:
(VA+) - (VA-) < 6.8 volts
(VD) - (VA-) < 7.6 volts
These conditions permit several power supply con-
figurations.
VA+ = +5V; VA- = 0V; VD+ = +3.3V to +5V
VA+ = +2.5V;VA- = -2.5V; VD+ = +3.3V
When used with the CS5376A or CS5378 digital fil-
ter the maximum voltage differential between the
modulator digital supply, VD, and the CS5376A/78
I/O supply, VDD2 or VDDPAD, must be 0.3V or
less.
9.2. Power Supply Bypassing
The analog and digital supply pins, VA+, VA-, and
VD, should be decoupled to system ground with
0.01 µF and 10 µF capacitors, or with a single
0.1 µF capacitor. Bypass capacitors can be X7R,
tantalum, or any other dielectric types.
