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ISL37231DRAZ-TS

P1-P3P4-P6P7-P9
ISL37231
4
FN8266.1
January 25, 2013
AIN2[P,N] A32, A33 Input
High-speed differential input for on-ramp (PCB to cable) Channel 2, CML. The use of series
220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.
AOUT2[N,P] A35, A36 Output High-speed differential output for on-ramp (PCB to cable) Channel 2, CML. (Note 4)
AOUT1[P,N] A39, A40 Output High-speed differential output for on-ramp (PCB to cable) Channel 1, CML. (Note 4)
AVDD1
B2, R1, R2, R3, R4
(Note 5)
1.0V analog supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground
is recommended for each of these pins/rails for broad high-frequency noise suppression.
AVDD18 B3
1.8V analog supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground
is recommended for this pin for broad high-frequency noise suppression.
NC
B4, B6, B7, B13, B14,
B19, B20, B26, B27
No connection. Do not connect to these pins.
DVDD B5, B15
1.0V digital supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground
is recommended for these pins for broad high-frequency noise suppression.
VDDPLLB1 B8 1.8V analog supply voltage for off-ramp Channel 1.
REFRETB1 B9 VDDPLL reference return path for off-ramp Channel 1.
REXT2 B10 External reference resistor connection. Recommended value of 1.18kΩ.
REFRETB2 B11 VDDPLL reference return path for off-ramp Channel 2.
VDDPLLB2 B12 1.8V analog supply voltage for off-ramp Channel 2.
AURX2 B16 Input Auxiliary UART input 2. CMOS logic, 1.8V (tolerant to 3.3V).
VDDPST B17
1.8V digital supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground
is recommended for each of these pins for broad high-frequency noise suppression.
RESET
B18 Input CMOS logic input. 1.8V powered. Resets all internal registers and memory when pulled low.
VDDPLLA2 B21 1.8V analog supply voltage for on-ramp Channel 2.
REFRETA2 B22 VDDPLL reference return path for on-ramp Channel 2.
REXT1 B23 External reference resistor connection. Recommended value of 1.18kΩ.
REFRETA1 B24 VDDPLL reference return path for on-ramp Channel 1.
VDDPLLA1 B25 1.8V analog supply voltage for on-ramp Channel 1.
NOTES:
4. Series coupling capacitors are required at one end of the cable. For best results, place the capacitors at the receiver end of the cable. The use of
220nF low ESL/ESR MLCC capacitors with at least 8GHz frequency response is recommended.
5. Each power bar is independent, so they must all connect to the same 1V supply for proper circuit operation.
Pin Functions and Definitions (Continued)
PIN NAME PIN NUMBER DIRECTION DESCRIPTION
ISL37231
5
FN8266.1
January 25, 2013
Absolute Maximum Ratings Thermal Information
Supply Voltage (V
DD
to GND, 1.0V Rails) . . . . . . . . . . . . . . . . . . . . . . . . 1.1V
Supply Voltage (V
DD
to GND, 1.8V Rails) . . . . . . . . . . . . . . . . . . . . . . . 1.98V
1V Pin Input Voltage (AIN, BIN, XTALP) . . . . . . . . . . . . . . . . . . . . . . . . . 1.1V
1.8V Pin Input Voltage (all non 3.3V tolerant logic inputs) . . . . V
DD
+ 0.2V
3.3V Tolerant I/O Pin Voltage (EEWE, SCLK, SDA, URX, AUTX, AURX,
RESET
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
ESD Ratings
Human Body Model (All Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25kV
Charged Device Model (All Pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV
Machine Model (All Pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Latch-up (per JEDEC JESD78, Level 2, Class A) . . . . . . . . . . . . . . . . +85°C
Thermal Resistance (Typical) θ
JA
(°C/W) θ
JC
(°C/W)
69 Ld aQFN Package (Notes 6, 7) . . . . . . . 31.8 2.5
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . 0°C to +85°C
Storage Ambient Temperature Range. . . . . . . . . . . . . . . -55°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTE:
6. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
.
7. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Operating Conditions Boldface limits apply across the operating temperature range, 0°C to +85°C.
PARAMETER SYMBOL CONDITION
MIN
(Note 12) TYP
MAX
(Note 12) UNITS
1.0V Supply Voltage AVDD1,
DVDD
0.95 1.0 1.05 V
1.8V Supply Voltage AVDD18,
VDDPLL,
VDDPST
1.71 1.8 1.89 V
Operating Ambient Temperature T
A
0 25 85 °C
Baud Rate NRZ data applied to any channel 9.95 10.3125 10.4 Gbps
Logic I/O Specifications Boldface limits apply across the operating temperature range, 0°C to +85°C.
PARAMETER SYMBOL CONDITION
MIN
(Note 12) TYP
MAX
(Note 12) UNITS
Input Leakage Current I
LEAK
Pins URX, AURX1, AURX2, RESET -1 0.1 1 µA
Pull-down Resistor Current I
PULLDOWN
OSCMODE. V
IN
= V
DD18
103 µA
Input HIGH Voltage V
IH
Pins URX, AURX1, AURX2, RESET,
OSCMODE
23.4V
Input LOW Voltage V
IL
Pins URX, AURX1, AURX2, RESET,
OSCMODE
00.7V
Output LOW Voltage V
OL
I
OL
= 2mA 00.4V
Output High Voltage V
OH
I
OH
= 2mA 1.4 V
DD18
V
ISL37231
6
FN8266.1
January 25, 2013
Electrical Characteristics T
A
= +25°C, V
DD1
= 1.0V, V
DD18
= 1.8V, unless otherwise noted
PARAMETERS SYMBOL CONDITION
MIN
(Note 12) TYP
MAX
(Note 12) UNITS NOTES
1.0V Supply Current
(Combination of all 1V
Supplies)
I
DD1
Both lanes active, after equalizer has trained
and is static, no eye monitors enabled
430 510 mA
No lanes active, but microcontroller awake 85 150 mA
Sleep Mode 4 mA 8
1.8V Supply Current
(Combination of all 1.8V
Supplies)
I
DD18
Both lanes active, after equalizer has trained
and is static, no eye monitors enabled
25
55 mA
No lanes active, but microcontroller awake 9 20 mA
Sleep Mode 330 µA 8
Return Loss Limit
(Differential)
S
DD
11
S
DD
22
0.05GHz to 2GHz -10 dB 9
2GHz to 5.2GHz -6 dB 9
5.2GHz to 7GHz -5 dB 9
Return Loss Limit (Common
Mode)
S
CC
11
S
CC
22
10MHz to 5GHz
-5
dB 9
Return Loss Limit (Diff. to
Com. Conversion)
S
CD
11
S
CD
22
10MHz to 5GHz
-20
dB 9
Input Equalization Range EQ gain at 5GHz compared to DC. Set to
minimum gain
6
dB 10
EQ gain at 5GHz compared to DC. Set to
maximum gain
16.5
dB 10
Input Equalization
Increment
10 steps covering the Equalization range
1.5
dB
Output De-Emphasis Level
Range
Off-ramp channels optimized for PCB
dielectric loss. On-ramp channels optimized
for cable skin loss. Minimum setting
0
dB
Off-ramp channels optimized for PCB
dielectric loss. On-ramp channels optimized
for cable skin loss. Maximum setting
9
dB
De-Emphasis Increment 1dB
Number of De-Emphasis
Taps
3
11
Output Differential
Amplitude Range
V
OUT
Minimum drive setting 200 mV
P-P
Maximum drive setting 950 mV
P-P
Output Differential
Amplitude Increment
15 Uniform Steps
50
mV
P-P
Output Transition Time t
r
, t
f
20% to 80% 45 ps
Jitter Transfer Function
Bandwidth
5
MHz
Total Output Jitter 1E-13 BER; PRBS-31; no low frequency input
periodic jitter
0.3
UI
P-P
SSC Down Spreading
Amplitude Tolerance
0.5
%
SSC Modulation Rate
Tolerance
33-37
kHz
NOTES:
8. The specified Sleep Mode currents can only be achieved when the ISL37231 is used in conjunction with the ISL80083 power management IC.
9. Measured with a Vector Network Analyzer with 100Ω -diff impedance and the ISL37231 input/output impedance at setting 0x07 (i.e. 100Ω-diff).
10. The equalization response includes all effects starting from the IC input pins up to the output of the equalization stage.
11. Three de-emphasis taps composed of: 1 pre-cursor + main + 1 post-cursor.
12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
P1-P3P4-P6P7-P9

ISL37231DRAZ-TS

Mfr. #:
Buy ISL37231DRAZ-TS
Manufacturer:
Renesas / Intersil
Description:
Equalizers 10.3125Gbs Retiming Dual-Ch Transceiver
Lifecycle:
New from this manufacturer.
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