For example: To minimize power loss on this resistor, choose a high-
er value for R1 than the one calculated above (if a
longer startup time can be tolerated).
The above startup method applies to a circuit similar to
the one shown in Figure 1. In this circuit, the tertiary
winding has the same phase as the secondary wind-
ings. Thus, the voltage on the tertiary winding at any
given time is proportional to the output voltage. The
minimum discharge time of C1 from 22V to 10V must
be greater than the soft-start time (t
SS
).
I
Vx F
ms
A
R
VV
AA
k
C1
24 4 7
500
225
1
36 12
225 90
76
.
==
+
=
µ
µ
µµ
MAX5069
High-Frequency, Current-Mode PWM Controller
with Accurate Oscillator and Dual FET Drivers
______________________________________________________________________________________ 13
IN
UVLO/EN
NDRVA
NDRVB
V
CC
FB
CS
PGNDAGND
REG5
FLTINT
RT
DT
SCOMP
COMP
HYST
R1
C1
C2
C3
C4
R2
R3
R4
C5
R6
R7
R5
R8
V
OUT
V
IN
Q2
Q1
C6
R
HYST
C7
C8
R9
C10
MAX8515
R13
R14
PS2913
V
CC
R10
R11
R12
MAX5069B
Figure 6. Secondary-Side, Regulated, Isolated Power Supply
MAX5069
Oscillator/Switching Frequency
Use an external resistor at RT to program the MAX5069
internal oscillator frequency from 50kHz to 2.5MHz. The
MAX5069 NDRVA/NDRVB switching frequency is one
half of the programmed oscillator frequency with a
maximum 50% duty cycle.
Use the following formula to calculate the internal oscil-
lator frequency:
where f
OSC
is the oscillator frequency and R
RT
is a
resistor connected from RT to AGND.
Choose the appropriate resistor at RT to calculate the
desired switching frequency (f
SW
):
For the maximum 50% duty cycle at NDRVA/NDRVB,
connect DT to REG5.
Dual N-Channel MOSFET Switch Driver
The MAX5069 drives two external N-channel MOSFETs
in push-pull isolated power supplies. Each MOSFET
driver operates with a maximum 50% duty cycle. The
NDRV_ outputs are supplied by the internal regulator
(V
CC
), which is internally set to approximately 9.5V. For
the universal input voltage range, the MOSFETs used
must be able to withstand at least twice the DC level of
the high-line input voltage. Both NDRVA and NDRVB
can source and sink in excess of 650mA and 1000mA
peak current, respectively.
Dead-Time Control
In typical push-pull designs, it is desirable to add some
extra delay between the turning off of one MOSFET and
the turning on of the next MOSFET (Figure 7). The extra
time ensures that the first MOSFET is fully off when the
other MOSFET starts to turn on. This prevents both
MOSFETs from being on simultaneously, thus avoiding
shorting out the transformer’s primary. The MAX5069
allows the dead-time delay required to turn on the
NDRVB FET after the NDRVA FET turns off. The dead
time can be programmed to a minimum of 30ns to 1 / (0.5
x f
SW
). Connect a resistor between DT and AGND to set
the desired dead time. Calculate the dead time using the
following formula:
where R
DT
is in k and the dead time is in ns.
External Synchronization (MAX5069A/D)
The MAX5069A/D can be synchronized using an exter-
nal clock at the SYNC input. For proper frequency syn-
chronization, the SYNC’s input frequency must be at
least 25% higher than the MAX5069A/D programmed
internal oscillator frequency. Connect SYNC to AGND
when not using an external clock.
Integrating Fault Protection
The integrating fault-protection feature allows transient
overcurrent conditions to be ignored for a programma-
ble amount of time, giving the power supply time to
behave like a current source to the load. For example,
this can occur under load-current transients when the
control loop requests maximum current to keep the out-
put voltage from going out of regulation. Program the
fault-integration time by connecting an external suitably
sized capacitor to the FLTINT. Under sustained over-
current faults, the voltage across this capacitor ramps
up towards the FLTINT shutdown threshold (typically
2.8V). Once the threshold is reached, the power supply
shuts down. A high-value bleed resistor connected in
parallel with the FLTINT capacitor allows it to discharge
towards the restart threshold (typically 1.6V). Once this
threshold is reached, the supply restarts with a new
soft-start cycle.
Dead time R ns
DT
.
()
60
29 4
RT
SW
R
f
=
10
2
11
f
R
osc
RT
=
10
11
High-Frequency, Current-Mode PWM Controller
with Accurate Oscillator and Dual FET Drivers
14 ______________________________________________________________________________________
DEAD TIME
NDRVA
PWM
PWM
<50%
<50%
NDRVB
t
DT
Figure 7. MAX5069 Dead-Time Timing Diagram
MAX5069A/D
AGND
RT
SYNC
Figure 8. External Synchronization of the MAX5069A/D
Note that cycle-by-cycle current limiting is provided at
all times by CS with a threshold of 314mV (typ). The
fault-integration circuit forces a 60µA current onto
FLTINT each time that the current-limit comparator is
tripped (see the Functional Diagram). Use the following
formula to calculate the value of the capacitor neces-
sary for the desired shutdown time of the circuit:
where I
FLTINT
= 60µA, t
SH
is the desired fault-integra-
tion time during which current-limit events from the cur-
rent-limit comparator are ignored. For example, a 0.1µF
capacitor gives a fault-integration time of 4.7ms.
This is an approximate formula. Some testing may be
required to fine-tune the actual value of the capacitor. To
calculate the recovery time, use the following formula:
where t
RT
is the desired recovery time.
Choose t
RT
= 10 x t
SH
. Typical values for t
SH
range from
a few hundred microseconds to a few milliseconds.
Soft-Start
The MAX5069 soft-start feature allows the load voltage
to ramp up in a controlled manner, eliminating output-
voltage overshoot. Soft-start begins after UVLO is
deasserted. The voltage applied to the noninverting
node of the amplifier ramps from 0 to 1.23V in 2047
oscillator clock cycles (soft-start timeout period). Unlike
other devices, the MAX5069 reference voltage to the
internal amplifier is soft-started. This method results in
superior control of the output voltage under heavy- and
light-load conditions.
Internal Regulators
Two internal linear regulators power the MAX5069 inter-
nal and external control circuits. V
CC
powers the exter-
nal N-channel MOSFETs and is internally set to
approximately 9.5V. The REG5 5V regulator has a 1mA
sourcing capability and may be used to provide power
to external circuitry. Bypass V
CC
and REG5 with 1µF
and 0.1µF high quality capacitors, respectively. Use
lower value ceramics in parallel to bypass other
unwanted noise signals. Bootstrapped operation
requires startup through a bleed resistor. Do not exces-
sively load the regulators while the MAX5069 is in the
power-up mode. Overloading the outputs may cause
the MAX5069 to fail upon startup.
Error Amplifier
The MAX5069 includes an internal error amplifier that
can regulate the output voltage in the case of a noniso-
lated power supply (Figure 1). Calculate the output volt-
age using the following equation:
where V
REF
= 1.23V. The amplifier’s noninverting input
internally connects to a digital soft-start reference voltage.
This forces the output voltage to come up in an orderly
and well-defined manner under all load conditions.
Slope Compensation
The MAX5069 uses an internal-ramp generator for
slope compensation. The internal-ramp signal resets at
the beginning of each cycle and slews at the rate pro-
grammed by the external capacitor connected at
SCOMP and the resistor at RT. Adjust the MAX5069
slew rate up to 90mV/µs using the following equation:
where R
RT
is the external resistor at RT that sets the oscil-
lator frequency and C
SCOMP
is the capacitor at SCOMP.
PWM Comparator
The PWM comparator uses the instantaneous current,
the error amplifier, and the slope compensation to
determine when to switch NDRVA and NDRVB off. In
normal operation, the N-channel MOSFETs turns off
when:
I
PRIMARY
x R
CS
> V
EA
– V
OFFSET
- V
SCOMP
where I
PRIMARY
is the current through the N-channel
MOSFETs, V
EA
is the output voltage of the internal
amplifier, V
OFFSET
is the 1.6V internal DC offset, and
V
SCOMP
is the ramp function starting at zero and slew-
ing at the programmed slew rate (SR). When using the
MAX5069 in a forward-converter configuration, the fol-
lowing conditions must be met to avoid current-loop
subharmonic oscillations:
where K = 0.75 and N
S
and N
P
are the number of turns
on the secondary and primary side of the transformer,
respectively. L is the secondary filter inductor. When
optimally compensated, the current loop responds to
input-voltage transients within one cycle.
S
P
CS OUT
N
N
K
RV
L
SR
×
××
=
SR
RC
mV s
RT SCOMP
(/)=
×
×
165 10
6
µ
V
R
R
xV
OUT REF
=+
1
9
10
R
t
C
FLTINT
RT
FLTINT
.
×0 595
C
Ixt
V
FLTINT
FLTINT SH
.
28
MAX5069
High-Frequency, Current-Mode PWM Controller
with Accurate Oscillator and Dual FET Drivers
______________________________________________________________________________________ 15

MAX5069AAUE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers High-Frequency Current-Mode PWM
Lifecycle:
New from this manufacturer.
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