MAX5069
MAX5069A/B Startup Operation
Normally, V
IN
is derived from the tertiary winding of the
transformer. However, at startup there is no energy
delivered through the transformer; hence, a special
bootstrap sequence is required. Figure 5 shows the
voltages on V
IN
and V
CC
during startup. Initially, both
V
IN
and V
CC
are 0V. After the input voltage is applied,
C1 charges through the startup resistor, R1, to an inter-
mediate voltage (see Figure 1). At this point, the inter-
nal regulator begins charging C3 (see Figure 5). Only
47µA of the current supplied by R1 is used by the
MAX5069A/B. The remaining input current charges C1
and C3. The charging of C3 stops when the V
CC
volt-
age reaches approximately 9.5V. The voltage across
C1 continues rising until it reaches the wake-up level of
23.6V. Once V
IN
exceeds the bootstrap UVLO thresh-
old, NDRVA/NDRVB begin switching the MOSFETs and
energy is transferred to the secondary and tertiary out-
puts. If the voltage on the tertiary output builds to high-
er than 9.74V (the bootstrap UVLO lower threshold),
startup ends and sustained operation commences.
If V
IN
drops below 9.74V before startup is complete, the
device goes back to low-current UVLO. If this occurs,
increase the value of C1 to store enough energy to
allow for the voltage at the tertiary winding to build up.
Startup Time Considerations for
Power Supplies Using the MAX5069A/B
The V
IN
bypass capacitor, C1, supplies current imme-
diately after wakeup (see Figure 1). The size of C1 and
the connection configuration of the tertiary winding
determine the number of cycles available for startup.
Large values of C1 increase the startup time and also
supply extra gate charge for more cycles during initial
startup. If the value of C1 is too small, V
IN
drops below
9.74V because NDRVA/NDRVB do not have enough
time to switch and build up sufficient voltage across the
tertiary output that powers the device. The device goes
back into UVLO and does not start. Use low-leakage
capacitors for C1 and C3.
Generally, offline power supplies keep typical startup
times to less than 500ms, even in low-line conditions
(85VAC input for universal offline applications or
36VDC for telecom applications). Size the startup resis-
tor, R1, to supply both the maximum startup bias of the
device (90µA) and the charging current for C1 and C3.
The bypass capacitor, C3, must charge to 9.5V, and
C1 must charge to 24V, within the desired time period
of 500ms. Because of the internal soft-start time of the
MAX5069, C1 must store enough charge to deliver cur-
rent to the device for at least 2047 oscillator clock
cycles. To calculate the approximate amount of capaci-
tance required, use the following formula:
where I
IN
is the MAX5069’s internal supply current after
startup (3.3mA, typ), Q
gtot
is the total gate charge for
Q1 and Q2, f
SW
is the MAX5069’s programmed output
switching frequency, V
HYST
is the bootstrap UVLO hys-
teresis (12V), and t
ss
is the internal soft-start time (2047
clock cycles x 1 / f
OSC
).
Example: I
g
= (16nC) (250kHz) ≅ 4mA
f
OSC
= 500kHz
t
SS
= 2047 x (1 / f
OSC
) = 4.1ms
Use a 4.7µF ceramic capacitor for C1.
Assuming C1 > C3, calculate the value of R1 as follows:
where V
SUVR
is the bootstrap UVLO wakeup level
(23.6V max), V
IN(MIN)
is the minimum input supply volt-
age for the application (36V for telecom), and I
START
is
the V
IN
supply current at startup (90µA, max).
