LT1246CS8#TRPBF Datasheet LT1246CS8#PBF, LT1246CN8#PBF, LT1247CS8#PBF | P7-P9

LT1246/LT1247

GND (Pin 5): Ground.

OUTPUT (Pin 6): Current Output. This pin is the output of

a high current totem pole output stage. It is capable of

driving up to ±1A of current into a capacitive load such as

the gate of a MOSFET.

(Pin 7): Supply Voltage. This pin is the positive supply

of the control IC.

REF

(Pin 8): Reference. This is the reference output of the

IC. The reference output is used to supply charging current

to the external timing resistor R

. The reference provides

biasing to a large portion of the internal circuitry, and is

used to generate several internal reference levels includ-

ing the V

level and the current sense clamp voltage.

I FOR ATIO

deadtime at that frequency. Curves of oscillator frequency

and deadtime for various values of R

and C

appear in the

Typical Performance Characteristics section. Frequency

and deadtime can also be calculated using the following

formulas:

Oscillator Rise Time: t

= 0.583 • RC

Oscillator Discharge Time:

Oscillator Period: t

OSC

= t

+ t

Oscillator Frequency:

Maximum Duty Cycle:

The above formulas will give values that will be accurate

to approximately ±5%, at the oscillator, over the full

operating frequency range. This is due to the fact that the

oscillator trip levels are constant versus frequency and the

discharge current and initial oscillator frequency are

trimmed. Some fine adjustment may be required to achieve

more accurate results. Once the final R

combination is

selected, the oscillator characteristics will be repeatable

from device to device. Note that there will be some slight

differences between maximum duty cycle at the oscillator

and maximum duty cycle at the output due to the finite rise

and fall times of the output.

Error Amplifier

The LT1246/LT1247 contain a fully compensated error

amplifier with a DC gain of 90dB and a unity-gain fre-

quency of 2MHz. Phase margin at unity-gain is 80°. The

noninverting input is internally committed to a 2.5V refer-

ence point derived from the 5V reference of pin 8. The

Minimum

Start-Up Operating Maximum

Device Threshold Voltage Duty Cycle Replaces

LT1246 16V 10V 100% UC1842

LT1247 8.4V 7.6V 100% UC1843

Oscillator

The LT1246/LT1247 are fixed frequency current mode

pulse width modulators. The oscillator frequency and the

oscillator discharge current are both trimmed and tightly

specified to minimize the variations in frequency and

deadtime. The oscillator frequency is set by choosing a

resistor and capacitor combination, R

and C

. This RC

combination will determine both the frequency and the

maximum duty cycle. The resistor R

is connected from

REF

(pin 8) to the R

pin (pin 4). The capacitor C

connected from the R

pin to ground. The charging

current for C

is determined by the value of R

. The

discharge current for C

is set by the difference between

the current supplied by R

and the discharge current of the

LT1246/LT1247. The discharge current of the device is

trimmed to 8.2mA. For large values of R

discharge time

will be determined by the discharge current of the device

and the value of C

. As the value of R

is reduced it will have

more effect on the discharge time of C

. During an oscil-

lator cycle capacitor C

is charged to approximately 2.8V

and discharged to approximately 1.1V. The output is

enabled during the charge time of C

and disabled, in an

off state, during the discharge time of C

. The deadtime of

the circuit is equal to the discharge time of C

. The

maximum duty cycle is limited by controlling the deadtime

of the oscillator. There are many combinations of R

and

that will yield a given oscillator frequency, however

there is only one combination that will yield a specific

•

−

346

0 0164 11 73

OSC

MAX

OSC

OSC d

OSC

−

LT1246/LT1247

I FOR ATIO

inverting input (pin 2) and the output (pin 1) are made

available to the user. The output voltage in a regulator

circuit is normally fed back to the inverting input of the

error amplifier through a resistive divider. The output of

the error amplifier is made available for external loop

compensation. The output current of the error amplifier is

limited to approximately 0.8mA sourcing and approxi-

mately 6mA sinking.

In a current mode PWM the peak switch current is a

function of the output voltage of the error amplifier. In the

LT1246/LT1247 the output of the error amplifier is offset

by two diodes (1.4V at 25°C), divided by a factor of three,

and fed to the inverting input of the current sense com-

parator. For output voltages less than 1.4V the duty cycle

of the output stage will be zero. The maximum offset that

can appear at the current sense input is limited by a 1V

clamp. This occurs when the error amplifier output reaches

4.4V at 25°C. The output of the error amplifier can be

clamped below 4.4V in order to reduce the maximum

voltage allowed across the current sensing resistor to less

than 1V. The supply current will increase by the value of

the output source current when the output voltage of the

error amplifier is clamped.

Current Sense Comparator and PWM Latch

LT1246/LT1247 are current mode controllers. Under nor-

mal operating conditions the output (pin 6) is turned on at

the start of every oscillator cycle, coincident with the rising

edge of the oscillator waveform. The output is then turned

off when the switch current reaches a threshold level

proportional to the error voltage at the output of the error

amplifier. Once the output is turned off it is latched off until

the start of the next cycle. The peak switch current is thus

proportional to the error voltage and is controlled on a

cycle by cycle basis. The peak switch current is normally

sensed by placing a sense resistor in the source lead of the

output MOSFET. This resistor converts the switch current

to a voltage that can be fed into the current sense input. For

normal operating conditions the peak inductor current,

which is equal to the peak switch current, will be equal to:

−

()

During fault conditions the maximum threshold voltage at

the input of the current sense comparator is limited by the

internal 1V clamp at the inverting input. The peak switch

current will be equal to:

PK MAX

(

)

10.

In certain applications such as high power regulators it

may be desirable to limit the maximum threshold voltage

to less than 1V in order to limit the power dissipated in the

sense resistor or to limit the short-circuit current of the

regulator circuit. This can be accomplished by clamping

the output of the error amplifier. A voltage level of

approximately 1.4V at the error amplifier output will give

a threshold voltage of 0V. A voltage level of approximately

4.4V at the output of the error amplifier will give a thresh-

old level of 1V. Between 1.4V and 4.4V the threshold

voltage will change by a factor of one third of the change

in the error amplifier output voltage. The threshold voltage

will be 0.333V for an error amplifier voltage of 2.4V. To

reduce the maximum current sense threshold to less than

1V the error amplifier output should be clamped to less

than 4.4V.

Blanking

A unique feature of the LT1246/LT1247 is the built-in

blanking circuit at the output of the current sense com-

parator. A common problem with current mode PWM

circuits is erratic operation due to noise at the current

sense input. The primary cause of noise problems is the

leading edge current spike due to transformer interwinding

capacitance and diode reverse recovery time. This current

spike can prematurely trip the current sense comparator

causing an instability in the regulator circuit. A filter at the

current sense input is normally required to eliminate this

instability. This filter will in turn slow down the current

sense loop. A slow current sense loop wil increase the

minimum pulse width which will increase the short-circuit

current in an overload condition. The LT1246/LT1247

blank (lock out) the signal at the output of the current

sense comparator for a fixed amount of time after the

switch is turned on. This prevents the PWM latch from

tripping due to the leading edge current spike. The blank-

ing time will be a function of the voltage at the feedback pin

(pin 2). The blanking time will be 60ns for normal operat-

LT1246/LT1247

I FOR ATIO

collector of the lower transistor, which is n-type silicon,

forms a p-n junction with the substrate of the device. The

substate of the device is tied to ground. This junction is

reverse biased during normal operation. In some applica-

tions the parasitic LC of the external MOSFET gate can ring

and pull the output pin below ground. If the output pin is

pulled negative by more than a diode drop, the parasitic

diode formed by the collector of the output NPN and the

substrate will turn on. This can cause erratic operation of

the device. In these cases a Schottky clamp diode is

recommended from output to ground.

Reference

The internal reference of the LT1246/LT1247 is a 5V

Bandgap reference, trimmed to within ±1% initial toler-

ance. The reference is used to power the majority of the

internal logic and the oscillator circuitry. The oscillator

charging current is supplied from the reference. The

feedback pin voltage and the clamp level for the current

sense comparator are derived from the reference voltage.

The reference can supply up to 20mA of current to power

external circuitry. Note that using the reference in this

manner, as a voltage regulator, will significantly increase

the power dissipation in the device, which will reduce the

operating ambient temperature range.

Design/Layout Considerations

LT1246/LT1247 are high speed circuits capable of gener-

ating pulsed output drive currents of up to 1A peak. The

rise and fall time for the output drive current is in the range

of 10ns to 20ns. High Speed circuit layout techniques

must be used to insure proper operation of the devices. Do

not attempt to use Proto-boards or wire-wrap tech-

niques to breadboard high speed switching regulator

circuits. They will not work properly.

Printed circuit layouts should include separate ground

paths for the voltage feedback network, oscillator capaci-

tor, and switch drive current. These ground paths should

be connected together directly at the ground pin (pin 5) of

the LT1246/LT1247. This will minimize noise problems

due to pulsed ground pin currents. V

should be by-

passed, with a minimum of 0.1µF, as close to the device

as possible. High current paths should be kept short and

they should be separated from the feedback voltage net-

work with shield traces if possible.

ing conditions (V

= 2.5V). The blanking time goes to zero

as the feedback pin is pulled to 0V. This means that the

blanking time will be minimized during start-up and also

during an output short-circuit fault. This blanking circuit

eliminates the need for an input filter at the current sense

input except in extreme cases. Eliminating the filter allows

the current sense loop to operate with minimum delays,

reducing peak currents during fault conditions.

Undervoltage Lockout

The LT1246/LT1247 incorporate an undervoltage lockout

comparator which prevents the internal reference circuitry

and the output from starting up until the supply voltage

reaches the start-up threshold voltage. The quiescent

current, below the start-up threshold, has been reduced to

less than 250µA (170µA typ.). This minimizes the power

loss due to the start-up resistor used in off-line converters.

In undervoltage lockout both V

REF

(pin 8) and the Output

(pin 6) are actively pulled low by Darlington connected

PNP transistors. They are designed to sink a few milliamps

of current and will pull down to about 1V. The pull-down

transistor at the reference pin can be used to reset the

external soft start capacitor. The pull-down transistor at

the output eliminates the external pull-down resistor re-

quired, with earlier devices, to hold the external MOSFET

gate low during undervoltage lockout.

Output

The LT1246/LT1247 incorporate a single high current

totem pole output stage. This output stage is capable of

driving up to ±1A of output current. Cross-conduction

current spikes in the output totem pole have been elimi-

nated. These devices are primarily intended for driving

MOSFET switches. Rise time is typically 30ns and fall time

is typically 20ns when driving a 1.0nF load. A clamp is built

into the device to prevent the output from rising above 18V

in order to protect the gate of the MOSFET switch. The

output is actively pulled low during undervoltage lockout

by a Darlington PNP. This PNP is designed to sink several

milliamps and will pull the output down to approximately

1V. This active pull-down eliminates the need for the

external resistor which was required in older designs.

The output pin of the device connects directly to the

emitter of the upper NPN drive transistor and the collector

of the lower NPN drive transistor in the totem pole. The

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LT1246CS8#TRPBF

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