74ACT174SCX

© 2000 Fairchild Semiconductor Corporation DS009935 www.fairchildsemi.com
November 1988
Revised October 2000
74AC174 • 74ACT174 Hex D-Type Flip-Flop with Master Reset
74AC174 74ACT174
Hex D-Type Flip-Flop with Master Reset
General Description
The AC/ACT174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all flip-
flops.
Features
I
CC
reduced by 50%
Outputs source/sink 24 mA
ACT174 has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74AC174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74ACT174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT174MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT174PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D
0
D
5
Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q
0
Q
5
Outputs
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74AC174 74ACT174
Functional Description
The AC/ACT174 consists of six edge-triggered D-type flip-
flops with individual D inputs and Q outputs. The Clock
(CP) and Master Reset (MR
) are common to all flip-flops.
Each D inputs state is transferred to the corresponding flip-
flops output following the LOW-to-HIGH Clock (CP) transi-
tion. A LOW input to the Master Reset (MR
) will force all
outputs LOW independent of Clock or Data inputs. The AC/
ACT174 is useful for applications where the true output
only is required and the Clock and Master Reset are com-
mon to all storage elements.
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Output
MR
CP D Q
LX X L
H
HH
H
LL
HL X Q
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74AC174 74ACT174
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Supply Voltage (V
CC
) 0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= 0.5V 20 mA
V
I
= V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) 0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= 0.5V 20 mA
V
= V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) 0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
) ±50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
) ±50 mA
Storage Temperature (T
STG
) 65°C to +150°C
Junction Temperature (T
J
)
PDIP 140
°C
Supply Voltage (V
CC
)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (V
I
)0V to V
CC
Output Voltage (V
O
)0V to V
CC
Operating Temperature (T
A
) 40°C to +85°C
Minimum Input Edge Rate (
V/t)
AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (
V/t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V 125 mV/ns
Symbol Parameter
V
CC
T
A
= +25°C T
A
= 40°C to +85°C
Units Conditions
(V) Typ Guaranteed Limits
V
IH
Minimum HIGH Level 3.0 1.5 2.1 2.1 V
OUT
= 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or V
CC
0.1V
5.5 2.75 3.85 3.85
V
IL
Maximum LOW Level 3.0 1.5 0.9 0.9 V
OUT
= 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or V
CC
0.1V
5.5 2.75 1.65 1.65
V
OH
Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V I
OUT
= 50 µA
5.5 5.49 5.4 5.4
V
IN
= V
IL
or V
IH
3.0 2.56 2.46 I
OH
= 12 mA
4.5 3.86 3.76 V I
OH
= 24 mA
5.5 4.86 4.76 I
OH
= 24 mA (Note 2)
V
OL
Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V I
OUT
= 50 µA
5.5 0.001 0.1 0.1
V
IN
= V
IL
or V
IH
3.0 0.36 0.44 I
OL
= 12 mA
4.5 0.36 0.44 V I
OL
= 24 mA
5.5 0.36 0.44 I
OL
= 24 mA (Note 2)
I
IN
Maximum Input
5.5 ±0.1 ±1.0 µA
V
I
= V
CC
(Note 4) Leakage Current or GND
I
OLD
Minimum Dynamic 5.5 75 mA V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3) 5.5 75 mA V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5 4.0 40.0 µA
V
IN
= V
CC
(Note 4) Supply Current or GND

74ACT174SCX

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC FF D-TYPE SNGL 6BIT 16SOIC
Lifecycle:
New from this manufacturer.
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