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73S8014RT-IL/F2
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P29
DS_8014R_012
73S8014R Data Sheet
Rev. 1.0
25
PIN
VDD
TTL
To
circuit
Pull-up
Disable
VERY
WEAK
PFET
ESD
VERY
WEAK
NFET
Pull-down
Enable
ESD
Note: Pins
CMDV
CC
,5V/
#V
, CLKDIV1 and CLKDIV2 have the pull-up enabled.
Pins RSTIN, CLKIN, PRES have the pull-do
wn enabled.
Figure 16: General Input Circuit
PIN
PIN
VDD
XTALIN
XTALOUT
ENABLEB
ENABLE
ESD
ESD
ESD
ESD
VERY
WEAK
FETs
STRONG
NFET
STRONG
NFET
STRONG
PFET
STRONG
PFET
Figure 17: Oscilla
tor Circuit
73S8014R Data Sheet
DS_8014R_012
26
Rev. 1.0
ESD
PIN
VDD
VDD FAULT
DETECTION
VREF = 1.400v
PIN
+
-
R = 60k
R = 40k
R = 0.4k
(approx
.)
VDDF_
ADJ
ESD
ESD
Figure 18: VDDF_ADJ
DS_8014R_012
73S8014R Data Sheet
Rev. 1.0
27
5
Mechanical Drawing
0.5050(12.82)
0.4065(10.32)
0.2960(7.51)
±
.0125(.318)
+ .003(.076)
- .004(.
101)
+ .005(.127
)
- .009(.22
8)
BASE PLANE
SEATING PLANE
0.5050(12.82)
0.0082
(.208)
0.1000
(2.54)
+ .004(.101)
- .007(.178)
0.016(.406)
0.050(1.27)
TYP
+ .004(.101)
- .003(.076)
+ .005(.127)
- .009(.228)
0
.
0
1
(
.2
5
4
)
+
.
0
0
2
5
(
.
0
6
3
4
)
-
.
0
0
1
0
(
.
0
2
5
4
)
Detail A
.033
(.838)
Detail “A”
0
°
- 8
°
±
.017(.431)
Figure 19: Mechanical Dra
w
ing 20-Pin SO Package
Inches (mm)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P29
73S8014RT-IL/F2
Mfr. #:
Buy 73S8014RT-IL/F2
Manufacturer:
Maxim Integrated
Description:
IC SMART CARD INTERFACE 20SOIC
Lifecycle:
New from this manufacturer.
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73S8014RT-IL/F2