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SCC2691AC1A28,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
Philips Semiconductors Product data sheet
SCC2691Universal asynchronous receiver/transmitter (UART)
2006 Aug 04
4
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
MNEMONIC
DIP PLCC
TYPE
NAME
AND
FUNCTION
D0–D7 22–15 27, 25,
24,
22–18
I Data Bus: Active-high 8-bit bidirectional 3-State data bus. Bit 0 is the LSB and bit 7 is the
MSB. All data, command, and status transfers between the CPU and the UART take place
over this bus. The direction of the transfer is controlled by the WRN and RDN inputs when
the CEN input is low. When the CEN input is high, the data bus is in the 3-State condition.
CEN 14 17 I Chip Enable: Active-low input. When low, data transfers between the CPU and the UART
are enabled on D0–D7 as controlled by the WRN, RDN and A0–A2 inputs. When CEN is
high, the UART is effectively isolated from the data bus and D0–D7 are placed in the 3-State
condition.
WRN 23 28 I Write Strobe: Active-low input. A low on this pin while CEN is low causes the contents of
the data bus to be transferred to the register selected by A0–A2. The transfer occurs on the
trailing (rising) edge of the signal.
RDN 1 2 I Read Strobe: Active-low input. A low on this pin while CEN is low causes the contents of
the register selected by A0–A2 to be placed on the data bus. The read cycle begins on the
leading (falling) edge of RDN.
A0–A2 8–6 11–9 I Address Inputs: Active-high address inputs to select the UART registers for read/write
operations.
RESET 11 14 I Reset: Master reset. A high on this pin clears the status register (SR), the interrupt mask
register (IMR), and the interrupt status register (ISR), sets the mode register pointer to MR1,
and places the receiver and transmitter in the inactive state causing the TxD output to go to
the marking (high) state. Clears Test modes.
INTRN 13 16 O Interrupt Request: This active-low output is asserted upon occurrence of one or more of
seven maskable interrupting conditions. The CPU can read the interrupt status register to
determine the interrupting condition(s). This open-drain output requires a pull-up resistor.
X1/CLK 9 12 I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate
frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal connections see
Figure 7, Clock Timing.
X2 10 13 I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin
not connected although it is permissible to ground it.
RxD 2 3 I Receiver Serial Data Input: The least significant bit is received first. If external receiver
clock is specified, this input is sampled on the rising edge of the clock.
TxD 3 4 O Transmitter Serial Data Output: The least significant bit is transmitted first. This output is
held in the marking (high) condition when the transmitter is idle or disabled and when the
UART is operating in local loopback mode. If external transmitter is specified, the data is
shifted on the falling edge of the transmitter clock.
MPO 4 5 O Multi-Purpose Output: One of the following functions can be selected for this output pin by
programming the auxiliary control register:
RTSN – Request to send active-low output. This output is asserted and negated via the
command register. By appropriate programming of the mode registers, RTSN can be pro-
grammed to be automatically reset after the character in the transmitter is completely shifted
or when the receiver FIFO and shift register are full.
C/TO – The counter/timer output.
TxC1X – The 1X clock for the transmitter.
TxC16X – The 16X clock for the transmitter.
RxC1X – The 1X clock for the receiver.
RxC16X – The 16X clock for the receiver.
TxRDY – The transmitter holding register empty signal. Active-low output. (Open drain)
RxRDY/FFULL – The receiver FIFO not empty/full signal. Active-low output. (Open drain)
MPI 5 6 I Multi-Purpose Input: This pin can serve as an input for one of the following functions:
GPI – General purpose input. The current state of the pin can be determined by reading the
ISR.
CTSN – Clear-to-send active-low input.
CTCLK – Counter/timer external clock input.
RTCLK – Receiver and/or transmitter external clock input. This may be a 1X or 16X clock as
programmed by CSR[3:0] or CSR[7:4].
Pin has an internal V
CC
pull-up device supplying 1 to 4 mA of current.
V
CC
24 1 I Power Supply: +5V supply input.
GND 12 15 I Ground
Philips Semiconductors Product data sheet
SCC2691Universal asynchronous receiver/transmitter (UART)
2006 Aug 04
5
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER RATING UNIT
T
A
Operating ambient temperature range
2
Note 4 °C
T
STG
Storage temperature range –65 to +150 °C
V
CC
Voltage from V
CC
to GND
3
–0.5 to + 7.0 V
V
S
Voltage from any pin to ground
3
–0.5 to V
CC
+10% V
P
D
Power Dissipation 300 mW
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperature, the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and V
CC
supply
range.
DC ELECTRICAL CHARACTERISTICS
1,
2,
3
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
Min Typ Max
UNIT
V
IL
V
IH
Input low voltage
Input high voltage
0.8 V
All except X1/CLK
X1/CLK
2
0.8V
CC
V
CC
V
V
V
OL
V
OH
4
Output low voltage
Output high voltage
(except open drain outputs)
I
OL
= 2.4mA
I
OH
= –400µA
2.4
0.4 V
V
I
IL
Input leakage current V
IN
= 0 to V
CC
–10 10 µA
I
LL
Data bus 3-State leakage current V
O
= 0.4 to V
CC
–10 10 µA
I
OD
Open-drain output leakage current V
O
= 0.4 to V
CC
–10 10
µA
I
XIL
X1/CLK low input current V
IN
= 0, X2 floated –100 –30 0 µA
I
XIH
X1/CLK high input current V
IN
= V
CC
, X2 floated 0 30 100 µA
I
X2L
X2 low output current V
OUT
= 0, X1/CLK = V
CC
–100 µA
I
X2H
X2 high output current V
OUT
= V
CC
, X1/CLK = 0V 100 µA
I
CCA
I
CCD
Power supply current, active
Power down current
5
0°C to +70°C
–40°C to +85°C
0.8
1.0
2.0
2.5
500
mA
mA
µA
NOTES:
1. Parameters are valid over specified temperature range. See Ordering Information table for applicable operating temperature and V
CC
supply
range.
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: C
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50pF, R
L
= 2.7kΩ to V
CC
.
5. For power down current levels in the 1µA region see the UART application note.
Philips Semiconductors Product data sheet
SCC2691Universal asynchronous receiver/transmitter (UART)
2006 Aug 04
6
AC ELECTRICAL CHARACTERISTICS
1,
2,
3,
4
SYMBOL
LIMITS
UNIT
SYMBOL
Min Typ Max
UNIT
Reset timing (Figure 3)
t
RES
Reset pulse width 100 ns
Bus timing (Figure 4)
5
t
AS
A0–A2 setup time to RDN, WRN low 10 ns
t
AH
A0–A2 hold time from RDN, WRN low 100 ns
t
CS
CEN setup time to RDN, WRN low 0 ns
t
CH
CEN hold time from RDN, WRN high 0 ns
t
RW
WRN, RDN pulse width 150 ns
t
DD
Data valid after RDN low 125 ns
t
DF
Data bus floating after RDN high 110 ns
t
DS
Data setup time before WRN high 50 ns
t
DH
Data hold time after WRN high 30 ns
t
RWD
Time between reads and/or writes
6,
7
150 ns
MPI and MPO timing (Figure 5)
5
t
PS
MPI input setup time before RDN low 30 ns
t
PH
MI input hold time after RDN low 30 ns
t
PD
MPO output valid after WRN high 370 ns
Interrupt timing (Figure 6)
t
IR
INTRN negated
Read RHR (RxRDY/FFULL interrupt) 370 ns
Write THR (TxRDY, TxEMT interrupt) 370 ns
Reset command (break change interrupt) 370 ns
Reset command (MPI change interrupt) 370 ns
Stop C/T command (counter interrupt) 370 ns
Write IMR (clear of interrupt mask bit) 270 ns
Clock timing (Figure 7)
t
CLK
X1/CLK high or low time 100 ns
f
CLK
9
X1/CLK frequency 0 4.0 MHz
t
CTC
Counter/timer clock high or low time 100 ns
f
CTC
8
Counter/timer clock frequency 0 4.0 MHz
t
RX
RxC high or low time 220 ns
f
RX
8
RxC frequency (16X)
RxC frequency (1X)
0
0
3.6864 2.0
1.0
MHz
MHz
t
TX
TxC high or low time 220 ns
f
TX
8
TxC frequency (16X)
TxC frequency (1X)
0
0
2.0
1.0
MHz
MHz
Transmitter timing (Figure 8)
t
TXD
TxD output delay from TxC external clock input on IP pin 350 ns
t
TCS
Output delay from TxC low at OP pin to TxD data output 0 150 ns
Receiver timing (Figure 9)
t
RXS
RxD data setup time before RxC high at external clock input on IP pin 100 ns
t
RXH
RxD data hold time after RxC high at external clock input on IP pin 100 ns
NOTES:
1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and V
CC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: C
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50pF, R
L
= 2.7kΩ to V
CC
.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed inter-
nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, this parameter defines the minimum high time between one CEN and the next. The RDN signal must
be negated for t
RWD
guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three rising edges of the X1 clock between writes.
8. These parameters are guaranteed by design, but are not 100% tested in production.
9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
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SCC2691AC1A28,518

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Buy SCC2691AC1A28,518
Manufacturer:
NXP Semiconductors
Description:
UART Interface IC UART
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