Philips Semiconductors Product data sheet
SCC2691Universal asynchronous receiver/transmitter (UART)
2006 Aug 04
8
values of CTUR and CTLR at any time, but the new count becomes
effective only on the next start counter command following a stop
counter command. If new values have not been loaded, the previous
count values are preserved and used for the next count cycle.
In the counter mode, the current value of the upper and lower eight
bits of the counter may be read by the CPU. It is recommended that
the counter be stopped when reading to prevent potential problems
which may occur if a carry from the lower eight bits to the upper
eight bits occurs between the times that both halves of the counter
are read. However, a subsequent start counter command causes
the counter to begin a new count cycle using the values in CTUR
and CTLR. See further description in CTUR/CTLR section.
Receiver and Transmitter
The UART is a full-duplex asynchronous receiver/transmitter. The
operating frequency for the receiver and transmitter can be selected
independently from the baud rate generator, the counter/timer, or
from an external input. Registers associated with the
communications channel are: the mode registers (MR1 and MR2),
the clock select register (CSR), the command register (CR), the
status register (SR), the transmit holding register (THR), and the
receive holding register (RHR).
Transmitter
The transmitter accepts parallel data from the CPU and converts it
to a serial bit stream on the TxD output pin. It automatically sends a
start bit followed by the programmed number of data bits, an
optional parity bit, and the programmed number of stop bits. The
least significant bit is sent first. Following the transmission of the
stop bits, if a new character is not available in the THR, the TxD
output remains high and the TxEMT bit in the SR will be set to 1.
Transmission resumes and the TxEMT bit is cleared when the CPU
loads a new character in the THR. In the 16X clock mode, this also
resynchronizes the internal 1X transmitter clock so that transmission
of the new character begins with minimum delay.
The transmitter can be forced to send a break (continuous low
condition) by issuing a start break command via the CR. The break
is terminated by a stop break command.
If the transmitter is disabled, it continues operating until the
character currently being transmitted and the character in the THR,
if any, are completely sent out. Characters cannot be loaded in the
THR while the transmitter is disabled.
Receiver
The receiver accepts serial data on the RxD pin, converts the serial
input to parallel format, checks for start bit, stop bit, parity bit (if any),
or break condition, and presents the assembled character to the
CPU. The receiver looks for a high-to-low (mark-to-space) transition
of the start bit on the RxD input pin. If a transition is detected, the
state of the RxD pin is sampled again each 16X clock for 7-1/2
clocks (16X clock mode) or at the next rising edge of the bit time
clock (1X clock mode). If RxD is sampled high, the start bit is invalid
and the search for a valid start bit begins again. If RxD is still low, a
valid start bit is assumed and the receiver continues to sample the
input at one bit time intervals at the theoretical center of the bit, until
the proper number of data bits and the parity bit (if any) have been
assembled, and one sop bit has been detected. The data is then
transferred to the RHR and the RxRDY bit in the SR is set to a 1. If
the character length is less than eight bits, the most significant
unused bits in the RHR are set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (i.e. framing error) and RxD remains low for
one-half of the bit period after the stop bit was sampled, then the
receiver operates as if a new start bit transition had been detected at
that point(one-half bit time after the stop bit was sampled).
The parity error, framing error and overrun error (if any) are strobed
into the SR at the received character boundary, before the RxRDY
status bit is set.
If a break condition is detected (RxD is low for the entire character
including the stop bit), only one character consisting of all zeros will
be loaded in the FIFO and the received SR break bit is set to 1. The
RxD input must return to high for two (2) clock edges of the X1
crystal clock for the receiver to recognize the end of the break
condition and begin the search for a start bit. This will usually
require a high time of one X1 clock period or 3 X1 edges since
the clock of the controller is not synchronous to the X1 clock.
RECEIVER FIFO
The RHR consists of a first-in-first-out (FIFO) queue with a capacity
of three characters. Data is loaded from the receive shift register
into the top-most empty position of the FIFO. The RxRDY bit in the
status register (SR) is set whenever one or more characters are
available to be read, and a FFULL status bit is set if all three queue
positions are filled with data. Either of these bits can be selected to
cause an interrupt. A read of the RHR outputs the data at the top of
the FIFO. After the read cycle, the data FIFO and its associated
status bits are ‘popped’ thus emptying a FIFO position for new data.
Receiver Status Bits
In addition to the data word, three status bits (parity error, framing
error, and received break) are appended to each data character in
the FIFO. Status can be provided in two ways, as programmed by
the error mode control bit in mode register 1. In the character mode,
status is provided on a character-by-character basis: the status
applies only to the character at the top of the FIFO. In the block
mode, the status provided in the SR for these three bits is the
logical-OR of the status for all characters coming to the top of the
FIFO since the last reset error command was issued. In either
mode, reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RHR is read. Therefore, the SR should be
read prior to reading the corresponding data character.
The receiver can control the deactivation of RTS. If programmed to
operate in this mode, the RTSN output will be negated when a valid
start bit was received and the FIFO is full. When a FIFO position
becomes available, the RTSN output will be re-asserted
automatically. This feature can be used to prevent an overrun, in
the receiver, by connecting the RTSN output to the CTSN input of
the transmitting device.
Receiver Reset and Disable
Receiver disable stops the receiver immediately – data being
assembled if the receiver shift register is lost. Data and status in the
FIFO is preserved and may be read. A re-enable of the receiver
after a disable will cause the receiver to begin assembling
characters at the next start bit detected. A receiver reset will discard
the present shift register data, reset the receiver ready bit (RxRDY),
clear the status of the byte at the top of the FIFO and re-align the
FIFO read/write pointers. This has the appearance of “clearing or
flushing” the receiver FIFO. In fact, the FIFO is NEVER cleared!
The data in the FIFO remains valid until overwritten by another
received character. Because of this, erroneous reading or extra
reads of the receiver FIFO will miss-align the FIFO pointers and
result in the reading of previously read data. A receiver reset will
re-align the pointers.
