LTC1553CSW#PBF Datasheet LTC1553CG#PBF, LTC1553CSW#PBF, LTC1553CSW#TRPBF | P10-P12

LTC1553

APPLICATIONS INFORMATION

WUU

OVERVIEW

The LTC1553 is a voltage feedback, synchronous switch-

ing regulator controller (see Block Diagram) designed for

use in high power, low voltage step-down (buck) convert-

ers. It is designed to satisfy the requirements of the Intel

Pentium II power supply specification. It includes an

on-chip DAC to control the output voltage, a PWM genera-

tor, a precision reference trimmed to ±1%, two high power

MOSFET gate drivers and all the necessary feedback and

control circuitry to form a complete switching regulator

circuit.

The LTC1553 includes a current limit sensing circuit that

uses the upper external power MOSFET as a current

sensing element, eliminating the need for an external

sense resistor. Once the current comparator, CC, detects

an overcurrent condition, the duty cycle is reduced by

discharging the soft start capacitor through a voltage-

controlled current source. Under severe overloads or

output short circuit conditions, the chip will be repeatedly

forced into soft start until the short is removed, preventing

the external components from being damaged. Under

output overvoltage conditions, the MOSFET drivers will be

disabled permanently until the chip power supply is

recycled or the OUTEN pin is toggled.

OUTEN can optionally be connected to an external nega-

tive temperature coefficient (NTC) thermistor placed near

the external MOSFETs or the microprocessor. Three thresh-

old levels are provided internally. When OUTEN drops to

2V, OT will trip, issuing a warning to the external CPU. If

the temperature continues to rise and the OUTEN input

drops to 1.7V, the G1 and G2 pins will be forced low. If

OUTEN is pulled below 1.2V, the LTC1553 will go into

shutdown mode, cutting the supply current to a minimum.

If thermal shutdown is not required, OUTEN can be con-

nected to a conventional TTL enable signal. The free-

running 300kHz PWM frequency can be synchronized to

a faster external clock connected to OUTEN. Adjusting the

oscillator frequency can add flexibility in the external

component selection. See the Clock Synchronization

section.

Output regulation can be monitored with the PWRGD pin

which in turn monitors the internal MIN and MAX com-

parators. If the output is ±5% beyond the selected value

for more than 500µs, the PWRGD output will be pulled

low. Once the output has settled within ±5% of the

selected value for more than 1ms, PWRGD will return

high.

THEORY OF OPERATION

Primary Feedback Loop

The regulator output voltage at the SENSE pin is divided

down internally by a resistor divider with a total resistance

of approximately 120kΩ. This divided down voltage is

subtracted from a reference voltage supplied by the DAC

output. The resulting error voltage is amplified by the error

amplifier and the output is compared to the oscillator ramp

waveform by the PWM comparator. This PWM signal

controls the external MOSFETs through G1 and G2. The

resulting chopped waveform is filtered by L

and C

OUT

closing the loop. Loop frequency compensation is achieved

with an external RC + C network at the COMP pin, which is

connected to the output node of the transconductance

amplifier.

MIN, MAX Feedback Loops

Two additional comparators in the feedback loop provide

high speed fault correction in situations where the ERR

amplifier may not respond quickly enough. MIN compares

the feedback signal FB to a voltage 60mV (5%) below the

internal reference. If FB is lower than the threshold of this

comparator, the MIN comparator overrides the ERR

amplifier and forces the loop to full duty cycle which is set

by the internal oscillator typically to 84%. Similarly, the

MAX comparator forces the output to 0% duty cycle if FB

is more than 5% above the internal reference. To prevent

these two comparators from triggering due to noise, the

MIN and MAX comparators’ response times are deliber-

ately controlled so that they take two to three microsec-

onds to respond. These two comparators help prevent

extreme output perturbations with fast output transients,

while allowing the main feedback loop to be optimally

compensated for stability.

LTC1553

APPLICATIONS INFORMATION

WUU

Soft Start and Current Limit

The LTC1553 includes a soft start circuit which is used for

initial start-up and during current limit operation. The SS

pin requires an external capacitor to GND with the value

determined by the required soft start time. An internal

10µA current source is included to charge the external SS

capacitor. During start-up, the COMP pin is clamped to a

diode drop above the voltage at the SS pin. This prevents

the error amplifier, ERR, from forcing the loop to maxi-

mum duty cycle. The LTC1553 will begin to operate at low

duty cycle as the SS pin rises above about 1.2V (V

COMP

≈

1.8V). As SS continues to rise, Q

turns off and the error

amplifier begins to regulate the output. The MIN compara-

tor is disabled when soft start is active to prevent it from

overriding the soft start function.

The LTC1553 includes yet another feedback loop to con-

trol operation in current limit. Just before every falling

edge of G1, the current comparator, CC, samples and

holds the voltage drop measured across the external

MOSFET, Q1, at the I

pin. Note that when V

= 12V, the

pin requires an external Zener to GND to prevent

voltage transients at the switching node between Q1 and

Q2 from damaging internal structures. CC compares the

voltage at I

to the voltage at the I

MAX

pin. As the peak

current rises, the measured voltage across Q1 increases

due to the drop across the R

DS(ON)

of Q1. When the voltage

at I

drops below I

MAX

, indicating that Q1’s drain current

has exceeded the maximum level, CC starts to pull current

out of the external soft start capacitor, cutting the duty

cycle and controlling the output current level. The CC

comparator pulls current out of the SS pin in proportion to

the voltage difference between I

and I

MAX

. Under minor

overload conditions, the SS pin will fall gradually, creating

a time delay before current limit takes effect. Very short,

mild overloads may not affect the output voltage at all.

More significant overload conditions will allow the SS pin

to reach a steady state, and the output will remain at a

reduced voltage until the overload is removed. Serious

overloads will generate a large overdrive at CC, allowing it

to pull SS down quickly and preventing damage to the

output components.

By using the R

DS(ON)

of Q1 to measure the output current,

the current limiting circuit eliminates an expensive dis-

crete sense resistor that would otherwise be required. This

helps minimize the number of components in the high

current path. Due to switching noise and variation of

DS(ON)

, the actual current limit trip point is not highly

accurate. The current limiting circuitry is primarily meant

to prevent damage to the power supply circuitry during

fault conditions. The exact current level where the limiting

circuit begins to take effect will vary from unit to unit as the

DS(ON)

of Q1 varies.

For a given current limit level, the external resistor from

MAX

to V

can be determined by:

IMAX

LMAX DS ON Q

IMAX

()( )

()1

where,

LMAX LOAD

RIPPLE

LOAD

= Maximum load current

RIPPLE

= Inductor ripple current

−

()()

()()()

VV V

fLV

IN OUT OUT

OSC O IN

OSC

= LTC1553 oscillator frequency = 300kHz

= Inductor value

DS(ON)Q1

= Hot on-resistance of Q1 at I

LMAX

IMAX

= Internal 180µA sink current at I

MAX

180µA

OUT

1553 F05

OUT

IMAX

–

20Ω

LTC1553

MAX

Figure 5. Current Limit Setting

LTC1553

Table 4. Recommended Minimum R

IMAX

Resistor (kΩ) vs Maximum Operating Load Current and External MOSFET Q1

MAXIMUM OPERATING SUD50N03-10 MTD20N03HDL

LOAD CURRENT (A) SUD50N03-10 (TWO IN PARALLEL) MTD20N03HDL (TWO IN PARALLEL)

12 2.4 1.2 4.3 2.2

14 2.7 1.3 5.1 2.7

16 3.0 1.5 6.2 3.0

18 3.6 1.8 6.8 3.3

20 3.9 2.0 7.5 3.6

APPLICATIONS INFORMATION

WUU

OUTEN and Thermistor Input

The LTC1553 includes a low power shutdown mode,

controlled by the logic at the OUTEN pin. A high at OUTEN

allows the part to operate normally. A low level at OUTEN

stops all internal switching, pulls COMP and SS to ground

internally and turns Q1 and Q2 off. OT and PWRGD are

pulled low, and FAULT is left floating. In shutdown, the

LTC1553 quiescent current will drop to about 130µA. The

remaining current is used to keep the thermistor sensing

circuit at OUTEN alive. Note that the leakage current of

the external MOSFETs may add to the total shutdown

current consumed by the circuit, especially at elevated

temperature.

OUTEN is designed with multiple thresholds to allow it to

also be utilized for over-temperature protection. The power

MOSFET operating temperature can be monitored with an

external negative temperature coefficient (NTC) thermistor

mounted next to the external MOSFET which is expected

to run the hottest––often the high-side device, Q1. Elec-

trically, the thermistor should form a voltage divider with

another resistor, R1, connected to V

. Their midpoint

should be connected to OUTEN (see Figure 6). As the

temperature increases, the OUTEN pin voltage is reduced.

Under normal operating conditions, the OUTEN pin should

stay above 2V. All circuits will function normally, and the

OT pin will remain in a high state. If the temperature gets

abnormally high, the OUTEN pin voltage will eventually

drop below 2V. OT will switch to a logic low, providing an

over-temperature warning to the system. As OUTEN drops

below 1.7V, the LTC1553 disables both FET drivers. If

Figure 6. OUTEN Pin as a Thermistor Input

OUT

1553 F06

OUT

5.6k

R2

NTC THERMISTOR

MOUNT IN CLOSE

THERMAL PROXIMITY

TO Q1

LTC1553

PENTIUM II

SYSTEM

OUTEN

OUTEN is less than 1.2V, the LTC1553 will enter shutdown

mode. To activate any of these three modes, the OUTEN

voltage must drop below the respective threshold for

longer than 30µs.

Clock Synchronization

The internal oscillator can be synchronized to an external

clock by applying the external clocking signal to the

OUTEN pin. The synchronizing range extends from the

initial operating frequency up to 500kHz. If the external

frequency is much higher than the natural free-running

frequency, the peak-to-peak sawtooth amplitude within

the LTC1553 will decrease. Since the loop gain is inversely

proportional to the amplitude of the sawtooth, the com-

pensation network may need to be adjusted slightly. Note

that the temperature sensing circuitry does not operate

when external synchronization is used.

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LTC1553CSW#PBF

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Description:

Switching Voltage Regulators 5-B Progmable Sync Sw Reg Cntr for Penti

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LTC1553CSW#PBF

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