SA571
http://onsemi.com
8
Variable Gain Cell
Figure 12 is a diagram of the variable gain cell. This is a
linearized two−quadrant transconductance multiplier. Q
1
,
Q
2
and the op amp provide a predistorted drive signal for the
gain control pair, Q
3
and Q
4
. The gain is controlled by I
G
and
a current mirror provides the output current.
Q
1
Q
2
Q
3
Q
4
NOTE:
I
2
(= 2I
1
)
280mA
I
G
I
IN
V
IN
R
2
20k
I
1
140mA
V+
V−
I
OUT
+
I
G
I
1
I
IN
+
I
G
V
IN
I
2
R
2
Figure 12. Simplified DG Cell Schematic
−
+
The op amp maintains the base and collector of Q
1
at
ground potential (V
REF
) by controlling the base of Q
2
. The
input current I
IN
(= V
IN
/R
2
) is thus forced to flow through
Q
1
along with the current I
1
, so I
C1
= I
1
+ I
IN
. Since I
2
has
been set at twice the value of I
1
, the current through Q
2
is:
I
2
− (I
1
+ I
IN
) = I
1
− I
IN
= I
C2
.
The op amp has thus forced a linear current swing between
Q
1
and Q
2
by providing the proper drive to the base of Q
2
.
This drive signal will be linear for small signals, but very
non−linear for large signals, since it is compensating for the
non−linearity of the differential pair, Q
1
and Q
2
, under large
signal conditions.
The key to the circuit is that this same predistorted drive
signal is applied to the gain control pair, Q
3
and Q
4
. When
two differential pairs of transistors have the same signal
applied, their collector current ratios will be identical
regardless of the magnitude of the currents. This gives us:
I
C1
I
C2
+
I
C4
I
C3
+
I
1
) I
IN
I
1
* I
IN
plus the relationships I
G
= I
C3
+ I
C4
and I
OUT
= I
C4
− I
C3
will
yield the multiplier transfer function,
I
OUT
+
I
G
I
1
I
IN
+
V
IN
R
2
I
G
I
1
This equation is linear and temperature−insensitive, but it
assumes ideal transistors.
If the transistors are not perfectly matched, a parabolic,
non−linearity is generated, which results in second
harmonic distortion. Figure 13 gives an indication of the
magnitude of the distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the
magnitude of the offset and the input level. Saturation of the
gain cell occurs at a +8 dBm level. At a nominal operating
level of 0 dBm, a 1.0 mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than
this, which means our overall offsets are typically about mV.
The distortion is not affected by the magnitude of the gain
control current, and it does not increase as the gain is
changed. This second harmonic distortion could be
eliminated by making perfect transistors, but since that
would be difficult, we have had to resort to other methods.
A trim pin has been provided to allow trimming of the
internal offsets to zero, which effectively eliminated second
harmonic distortion. Figure 14 shows the simple trim
network required.
3
2
1
.34
−6 0 +6
4mV
3mV
2mV
1mV
INPUT LEVEL (dBm)
% THD
Figure 13. DG Cell Distortion vs. Offset Voltage
3.6V
CC
R
6.2kW
To THD Trim
≈200pF
Figure 14. THD Trim Network
20kW
