MAX3690
+3.3V, 622Mbps, SDH/SONET 8:1 Serializer
with Clock Synthesis and TTL Inputs
4 _______________________________________________________________________________________
______________________________________________________________Pin Description
NAME FUNCTION
1–8 PD0–PD7 TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.
9, 10, 17,
18, 19, 24,
25, 26,
31, 32
GND Ground
PIN
11 PCLKO
TTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management
circuit.
12, 13, 16,
21, 28, 29
V
CC
+3.3V Supply Voltage
20 CKSET
Reference Clock Rate Programming Pin.
CKSET = open: Reference clock rate = 77.76MHz
CKSET = 20kΩ to GND: Reference clock rate = 51.84MHz
CKSET = GND: Reference clock rate = 38.88MHz
15 SD+ Noninverting PECL Serial-Data Output
14 SD- Inverting PECL Serial-Data Output
30 PCLKI
TTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The
active edge is the positive transitioning edge.
27 RCLK
TTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to
the RCLK input. The active edge is the positive transitioning edge.
23 FIL+ Filter Capacitor Input. Connect a 1µF capacitor between FIL- and V
CC
.
_______________Detailed Description
The MAX3690 serializer comprises an 8-bit parallel
input register, an 8-bit shift register, control and timing
logic, a PECL output buffer, TTL input/output buffers,
and a frequency-synthesizing PLL (consisting of a
phase/frequency detector, loop filter/amplifier, voltage-
controlled oscillator, and programmable prescaler).
This device converts 8-bit-wide, 77Mbps parallel data
to 622Mbps serial data (Figure 1).
The PLL synthesizes an internal 622MHz reference
used to clock the output shift register. This clock is
generated by locking onto the external crystal refer-
ence clock signal (RCLK) operating at either
77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-
allel data is clocked into the MAX3690 on the rising
transition of the parallel-clock-input signal (PCLKI). The
control and timing logic ensure proper operation if the
parallel-input register is latched within a window of time
that is defined with respect to the parallel-clock-output
signal (PCLKO). PCLKO is the synthesized 622MHz
internal serial-clock signal divided by eight. Parallel-
clock output to parallel-clock-input delay (skew) must
be observed. Figure 2 shows the timing diagram.
PECL Outputs
The serial-data PECL outputs (SD+, SD-) require 50Ω
DC termination to (V
CC
- 2V). See the Alternative PECL-
Output Termination section.
22 FIL- Filter Capacitor Input. Connect a 1µF capacitor between FIL- and V
CC
.
