xrxr XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
7
ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED
Parameter Symbol Min Typ Max Unit Conditions
D
IGITAL OUTPUT SPECIFICATIONS
Valid Output Logic Low
V
ol
0.5 V I
Sink
= 2.0mA, C
L
=10pf
Valid Output Logic High
V
oh
VDD-0.5 V I
Source
= 2.0mA, C
L
=10pf
Tristate Leakage IO
Leak
-10 0.1 +10 µA
Parameter Symbol Min Typ Max Unit Conditions
P
OWER SUPPLIES - 3 CHANNEL MODE
Analog Power Supply AVDD 3.0 3.3 3.6 V
Digital Power Supply DVDD 3.0 3.3 3.6 V
Analog IDD I
AVDD
30 57 70 mA AVDD = DVDD = 3.6V
Digital IDD I
DVDD
0.1 7 20 mA AVDD = DVDD = 3.6V
IDD Total IDD 31 64 90 mA AVDD = DVDD = 3.6V
Power Dissipation PD 112 230 325 mW AVDD = DVDD = 3.6V
Power Down Current IDD
PDN
0.2 1.3
Parameter Symbol Min Typ Max Unit Conditions
P
OWER SUPPLIES - 1 CHANNEL MODE
Analog Power Supply AVDD 3.0 3.3 3.6 V
Digital Power Supply DVDD 3.0 3.3 3.6 V
IDD Total IDD 40 mA AVDD = DVDD = 3.6V
Power Dissipation PD 145 mW AVDD = DVDD = 3.6V
Power Down Current IDD
PDN
0.2 1.3 mA
XRD9818 xrxr
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
8
ELECTRICAL CHARACTERISTICS (CONTINUED) - XRD9818
AVDD=DVDD=3.3V, ADCLK=12MHZ, PGA GAIN=MIN, PIXEL RATE=4MHZ, TA=25C UNLESS OTHERWISE SPECIFIED
Parameter Symbol Min Typ Max Unit Conditions
S
ERIAL PORT WRITE TIMING SPECIFICATIONS
Data Setup Time
Tds
10 ns
Data Hold Time
Tdh
10 ns
Load Setup Time
Tls
10
ns
Load Hold Time
Tlh
10 ns
SCLK Period
Tsclk
125 ns
Load Pulse High Period
Tlpw
125 ns 1 SCLK period
Parameter Symbol Min Typ Max Unit Conditions
T
IMING SPECIFICATIONS
ADCLK Duty Cycle daclk 50 %
ADCLK Period tcp3b
tcp3n
tcp2b
tcp2n
tcp1b
tcp1n
83.3
41.7
83.3
41.7
125
62.5
ns
ns
ns
ns
ns
ns
3-CH, 8bit (byte) output
3-CH, 4bit (nibble) output
2-CH, 8bit (byte) output
2-CH, 4bit (nibble) output
1-CH, 8bit (byte) output
1-CH, 4bit (nibble) output
Conversion Period tcr3
tcr2
tcr1
250
167
125
ns
ns
ns
3-Channel Mode
2-Channel Mode
1-Channel Mode
BSAMP Pulse Width tpwb 15 30 ns
VSAMP Pulse Width tpwv 15 30 ns
VSAMP
edge delay
from rising ADCLK
tvfcr 12 ns
Settling time tstl 15 ns
Aperture Delay tap 3 ns
Output Delay
todv
12 ns
Latency
lat
9
18
ADCLK
cycles
B/N=0 (byte mode)
B/N=1 (nibble mode)
xrxr XRD9818
3-CHANNEL 16-BIT LINEAR CCD/CIS SENSOR SIGNAL PROCESSOR
REV. 1.0.1
9
PRODUCT DESCRIPTION
1.0 INTRODUCTION
The XRD9818 contains all of the circuitry required to create a complete 3-channel signal processor/digitizer for
use in CCD/CIS imaging systems. It can be configured to operate in a 3-CH rotating (RGB), 2-CH rotating
(RG, GR, GB or BR), or a 1-CH fixed (R, G or B) mode.
Each channel includes a correlated-double-sampler/sample-hold (CDS/SH), channel offset adjustment and
programmable gain amplifier (PGA). After signal conditioning the channel outputs are multiplexed and digitized
by a 16-bit A/D converter.
The XRD9818 has selectable 8-bit (byte) or 4-bit (nibble) data output modes. The ADCLK runs up to 12MHz in
the 8-bit data output mode or 24MHz in the 4-bit data output mode.
In order to maximize flexibility, the specific operating mode is programmable through internal configuration
registers. In addition, the offset and gain of each channel can be independently programmed through separate
offset and gain registers. The configuration, offset and gain register information is loaded through a 3-pin serial
interface.
2.0 MODES OF OPERATION
2.1 3-CH CCD Mode
In 3-CH mode the XRD9818 simultaneously samples the red, green and blue channel inputs. The CDS
extracts the video information which corresponds to the difference between the sample black reference and
video level for each pixel. The black reference level is sampled on the falling edge of BSAMP and the video
level is sampled on the falling edge of VSAMP. This information is then level shifted and gained up according to
the contents of the Offset and PGA registers respectively. The data is then sequentially converted (Red
Green Blue) by a 16-bit A/D converter.
In CCD mode, each channel input is sampled with respect to the CMN- input. This provides a sudo-differential
input. Typically the CMN- input is connected to the CCD ground through a capacitor. This coupling capacitor
should be at least 3 times the capacitor value used to couple the RED+, GRN+ and BLU+ inputs.
The timing for this mode is shown in Figure15.
2.2 2-CH CCD Mode
The 2-CH mode operates identically to the 3-CH CCD mode except that only 2 channels are actively used to
process CCD output signals. The two channels to be used and the order in which they process data is
determined from the configuration of the Input-Mux/Channel-Select bits (CH[2:0]) located in the Mode 1
register. There are four possible 2-CH configurations, RG, GR, GB and BR. To conserve power that channel
not being utilized is powered down.
The timing for this mode is shown in Figure16.
2.3 1-CH CCD Mode
The 1-CH mode operates identically to the 3-CH or 2-CH CCD modes except that the channel sampled is fixed
to only one input. The channel selection is set by the Input-Mux/Channel-Select bits (CH[2:0]) located in the
Mode 1 register. There are three possible one channel modes: R, G or B. The channels not being used will be
powered down to conserve power.
The timing for this mode is shown in Figure17.

XRD9818ACGTR-F

Mfr. #:
Manufacturer:
MaxLinear
Description:
Analog to Digital Converters - ADC
Lifecycle:
New from this manufacturer.
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