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POWER MANAGEMENT
SC2621
Applications Information (Cont.)
Input CapacitorInput Capacitor
Input CapacitorInput Capacitor
Input Capacitor
The input capacitor should be chosen to handle the RMS
ripple current of a synchronous buck converter. This value
is given by:
22
)()1(
INoINRMS
IIDIDI -×+×-=
where Io is the load current, IIN is the input average cur-
rent, and D is the duty cycle. Choosing low ESR input
capacitors will help maximize ripple rating for a given size.
MOSFET for Linear RegulatorMOSFET for Linear Regulator
MOSFET for Linear RegulatorMOSFET for Linear Regulator
MOSFET for Linear Regulator
The MOSFET in linear regulator operates in linear region
with really high power loss. A device with a suitable pack-
age has to be selected to handle the loss. To prevent too
high load current during short circuit, the R
dson of the
MOSFET should not be selected too low. A good choice is
to select a MOSFET so that it is almost fully turned on at
maximum load current. For example, in a LDO design with
3.3V in and 1.5V/2A out, a MOSFET with 600 to 800m-
ohm Rdson can be chosen.
Bootstrap CircuitBootstrap Circuit
Bootstrap CircuitBootstrap Circuit
Bootstrap Circuit
The SC2621 uses an external bootstrap circuit to pro-
vide a voltage at BST pin for the top MOSFET drive. This
voltage, referring to the Phase Node, is held up by a
bootstrap capacitor. Typically, it is recommended to use
a 1uF ceramic capacitor with 16V rating and a commonly
available diode IN4148 for the bootstrap circuit.
Filters for Supply PowerFilters for Supply Power
Filters for Supply PowerFilters for Supply Power
Filters for Supply Power
For each pin of DRV and Vcc, it is recommended to use a
1uF/16V ceramic capacitor for decoupling. In addition,
place a small resistor (10 ohm) in between Vcc pin and
the supply power for noise reduction.
CONTROL LOOP DESIGNCONTROL LOOP DESIGN
CONTROL LOOP DESIGNCONTROL LOOP DESIGN
CONTROL LOOP DESIGN
The goal of compensation is to shape the frequency re-
sponse charateristics of the buck converter to achieve a
better DC accuracy and a faster transient response for
the output voltage, while maintaining the loop stability.
The block diagram in Fig. 3 represents the control loop
of a buck converter designed with the SC2621. The con-
trol loop consists of a compensator, a PWM modulator,
and a LC filter.
The LC filter and PWM modulator represent the small
signal model of the buck converter operating at fixed
switching frequency. The transfer function of the model
is given by:
LCsRsL
CsR
V
V
V
V
ESR
m
IN
C
O
2
/1
1
++
+
×=
where VIN is the power rail voltage, Vm is the amplitude
of the 500kHz ramp, and R is the equivalent load.
L Vo
Co
SC2621 AND MOSFETS
FB
OUT
COMP
PWM
MODULATOR
REF
+
-
EA
Resr
Zf
Zs
Vc
Fig. 3. Block diagram of the control loop
The model is a second order system with a finite DC gain,
a complex pole pair at Fo, and an ESR zero at Fz, as
shown in Fig. 4. The locations of the poles and zero are
determined by:
LC
F
O
1
=
CR
F
ESR
Z
1
=
The compensator in Fig. 3 includes an error amplifier and
impedance networks Zf and Zs. It is implemented by the
circuit in Fig. 5. The compensator provides an integrator,
double poles and double zeros. As shown in Fig. 4, the
integrator is used to boost the gain at low frequency.
Two zeros are introduced to compensate excessive phase
lag at the loop gain crossover due to the integrator
(-90deg) and complex pole pair (-180deg). Two high fre-
quency poles are designed to compensate the ESR zero
