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ISL89165FBEBZ-T

P1-P3P4-P6P7-P9P10-P12P13-P15
ISL89163, ISL89164, ISL89165
4
FN7707.5
October 13, 2016
Submit Document Feedback
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD
Relative to GND . . . . . . . . . . . . . . . . . . . -0.3V to 18V
Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to V
DD
+ 0.3V
Average Output Current (Note 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . 2000V
Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . 200V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Latch-Up
(Tested per JESD-78B; Class 2, Level A)
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Resistance (Typical)
JA
(°C/W)
JC
(°C/W)
8 Ld TDFN Package (Notes 6
, 7). . . . . . . . . 44 3
8 Ld EPSOIC Package (Notes 6
, 7). . . . . . . 42 3
Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W
Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . .33.3W
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Operating Junction Temp Range . . . . . . . . . . .-40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Options A and B
Supply Voltage, VDD Relative to GND . . . . . . . . . . . . . . . . . . .4.5V to 16V
Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Option C
Supply Voltage, VDD Relative to GND . . . . . . . . . . . . . . . . . . .7.5V to 16V
Logic Inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6.
JA
is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379
for details.
7. Fo r
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by trans conductance or r
DS(ON)
and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified
absolute maximum.
DC Electrical Specifications V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across
the operating junction temperature range, -40°C to +125°C.
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITMIN TYP MAX
MIN
(Note 9
)
MAX
(Note 9)
POWER SUPPLY
Voltage Range (Option A and B) V
DD
--- 4.5 16 V
Voltage Range (Option C) V
DD
--- 7.5 16 V
V
DD
Quiescent Current I
DD
ENx = INx = GND - 5 - - - mA
INA = INB = 1MHz, square wave - 25 - - mA
UNDERVOLTAGE
VDD Undervoltage Lock-out
(Options A and B) (Note 13
,
Figure 10
)
V
UV
ENA = ENB = True
INA = INB = True
-3.3- - - V
VDD Undervoltage Lock-out
(Option C) (Note 13
, Figure 10)
V
UV
ENA = ENB = True
INA = INB = True (Note 9)
-6.5- - - V
Hysteresis (Option A or B) - ~25 - - - mV
Hysteresis (Option C) - ~0.95 - - - V
ISL89163, ISL89164, ISL89165
5
FN7707.5
October 13, 2016
Submit Document Feedback
INPUTS
Input Range
for INA, INB, ENA, ENB
V
IN
Option A, B, or C - - -
GND V
DD
V
Logic 0 Threshold
for INA, INB, ENA, ENB
(Note 12
)
V
IL
Option A, nominally 37% x 3.3V - 1.22 - 1.12 1.32 V
Option B, nominally 37% x 5.0V - 1.85 - 1.70 2.00 V
Option C, nominally 20% x 12V
(Note 10
)
-2.4- 2.00 2.76 V
Logic 1 Threshold
for INA, INB, ENA, ENB
(Note 12
)
V
IH
Option A, nominally 63% x 3.3V - 2.08 - 1.98 2.18 V
Option B, nominally 63% x 5.0V - 3.15 - 3.00 3.30 V
Option C, nominally 80% x 12V
(Note 10
)
-9.6- 9.24 9.96 V
Input Capacitance of INA, INB,
ENA, ENB (Note 11
)
C
IN
-2- - - pF
Input Bias Current
for INA, INB, ENA, ENB
I
IN
GND < V
IN
< V
DD
--- -10 +10 µA
OUTPUTS
High Level Output Voltage V
OHA
V
OHB
---V
DD
- 0.1 V
DD
V
Low Level Output Voltage V
OLA
V
OLB
--- GND GND + 0.1 V
Peak Output Source Current I
O
V
O
(initial) = 0V, C
LOAD
= 10nF - -6 - - - A
Peak Output Sink Current I
O
V
O
(initial) = 12V, C
LOAD
= 10nF - +6 - - - A
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. The nominal 20% and 80% thresholds for option C are valid for any value within the specified range of VDD.
11. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
12. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted
inputs is less than the logic 0 threshold voltage.
13. A 400µs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 10 on page 8
.
DC Electrical Specifications V
DD
= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits apply across
the operating junction temperature range, -40°C to +125°C. (Continued)
PARAMETERS SYMBOL TEST CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITMIN TYP MAX
MIN
(Note 9
)
MAX
(Note 9)
ISL89163, ISL89164, ISL89165
6
FN7707.5
October 13, 2016
Submit Document Feedback
AC Electrical Specifications V
DD
= 12V, GND = 0V, No Load on OUTA or OUTB, unless otherwise specified. Boldface limits apply over
the operating junction temperature range, -40°C to +125°C.
PARAMETERS SYMBOL TEST CONDITIONS /NOTES
T
J
= +25°C T
J
= -40°C to +125°C
UNITMIN TYP MAX MIN MAX
Output Rise Time (see Figure 5
)t
R
C
LOAD
= 10nF,
10% to 90%
-20- - 40 ns
Output Fall Time (see Figure 5
)t
F
C
LOAD
= 10nF, 90% to 10% - 20 - - 40 ns
Output Rising Edge Propagation Delay for
Non-Inverting Inputs (Note 14
)
(see Figure 4
)
t
RDLYn
V
DD
= 12V
Options A and B
-25- - 50 ns
V
DD
= 8V
Option C
-25- - 50 ns
Output Rising Edge Propagation Delay with
Inverting Inputs (Note 14
)
(see Figure 4
)
t
RDLYi
V
DD
= 12V
Options A and B
-25- - 50 ns
V
DD
= 8V
Option C
-25- - 50 ns
Output Falling Edge Propagation Delay with
Non-Inverting Inputs (Note 14
)
(see Figure 4
)
t
FDLYn
V
DD
= 12V
Options A and B
-25- - 50 ns
V
DD
= 8V
Option C
-25- - 50 ns
Output Falling Edge Propagation Delay with
Inverting Inputs (Note 14
)
(see Figure 4
)
t
FDLYi
V
DD
= 12V
Options A and B
-25- - 50 ns
V
DD
= 8V
Option C
-25- - 50 ns
Rising Propagation Matching (see Figure 4
)t
RM
No load - <1 - - - ns
Falling Propagation Matching (see Figure 4)t
FM
No load - <1 - - - ns
Miller Plateau Sink Current
(See Test Circuit Figure 6
)
-I
MP
V
DD
= 10V,
V
MILLER
= 5V
-6- - - A
-I
MP
V
DD
= 10V, V
MILLER
= 3V - 4.7 - - - A
-I
MP
V
DD
= 10V, V
MILLER
= 2V - 3.7 - - - A
Miller Plateau Source Current
(See Test Circuit Figure 7
)
I
MP
V
DD
= 10V, V
MILLER
= 5V - 5.2 - - - A
I
MP
V
DD
= 10V, V
MILLER
= 3V - 5.8 - - - A
I
MP
V
DD
= 10V, V
MILLER
= 2V - 6.9 - - - A
Turn On Delay
(Note 13
, Figure 10)
T
on_delay
see Figure 10 400 µs
NOTE:
14. Propagation delays for option C are typically the same for the recommended operating range (7.5V ≤ V
DD
≤ 16V).
P1-P3P4-P6P7-P9P10-P12P13-P15

ISL89165FBEBZ-T

Mfr. #:
Buy ISL89165FBEBZ-T
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 6A PEAK HI SPD PWR MSFT DRVR 8LD EP
Lifecycle:
New from this manufacturer.
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