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MAX6879ETE+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
MAX6877/MAX6878/MAX6879
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
16 ______________________________________________________________________________________
Detailed Description
The MAX6877/MAX6878/MAX6879 multivoltage power
trackers/sequencers/supervisors monitor up to three
system voltages and provide proper power-up and
power-down control for systems requiring voltage
tracking or sequencing. These devices ensure con-
trolled voltage tracking with a specified range or
sequencing in the proper order as system power sup-
plies are enabled. The MAX6877/MAX6878/MAX6879
generate all required voltages and timing to control up
to three external n-channel pass FETs for the
OUT1/OUT2/OUT3 supply voltages (see the Selector
Guide for different features of each device.)
The MAX6877/MAX6878/MAX6879 feature adjustable
undervoltage thresholds for each input supply. When
all the voltages are above these adjusted thresholds,
the devices turn on the external n-channel MOSFETs to
either sequence or track the voltages to the system.
During the voltage-tracking mode, the voltage at the
GATE of each MOSFET is increased to slowly bring up
all supplies at a controlled slew rate. The voltage at the
source (output) of each MOSFET is internally compared
to a control ramp to maintain a low differential between
each monitored supply. Tracking is dynamically adjust-
ed to force all outputs to track within 125mV of the ref-
erence ramp. If for any reason any supplies fail to track
within ±250mV of the reference ramp, the FAULT out-
put is asserted, the power-up mode is terminated, and
all outputs are quickly powered off. In sequencing
mode, the outputs are turned on one after the other,
OUT1 first and OUT3 last. The MAX6877/MAX6878/
MAX6879 feature an autoretry or latch-off mode with
capacitor-adjusted timing.
These devices also provide a controlled power-down
(tracking mode) when the system shuts off in an orderly
manner. When an unexpected fault occurs, the outputs
are all pulled down simultaneously with an internal
100Ω pulldown to help discharge capacitive loads at
the MOSFET’s source.
The MAX6877/MAX6878/MAX6879 feature independent
internal charge pumps to fully enhance the external
FETs for low-voltage drops at highpass currents. The
MAX6877/MAX6878 also feature a power-good output
with a selectable timeout period that can be used for
system reset.
The MAX6877/MAX6878/MAX6879 monitor up to three
voltages. Devices may be configured to exclude any
IN_. To disable the tracking or sequencing operation of
any IN_, connect the IN_ to ground (or leave uncon-
nected) and connect SET_ to a voltage greater than
0.5V. The channel exclusion feature adds more flexibili-
ty to the device in a variety of different applications. As
an example, the MAX6877 can track or sequence two
voltages using IN1 and IN2 while IN3 is left disabled.
Powering the
MAX6877/MAX6878/MAX6879
These devices derive power from either the IN1, IN2, or
IN3 voltage inputs or V
CC
(see the Functional Diagram).
V
CC
or one of the IN_ inputs must be at least +2.7V to
ensure full device operation.
The highest input voltage on IN1/IN2/IN3 or V
CC
sup-
plies power to the devices. Internal hysteresis ensures
that the supply input that initially powers these devices
continues to power the MAX6877/MAX6878/MAX6879
when multiple input voltages are within 100mV (typ) of
each other.
ABP
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. ABP takes the highest voltage of
IN_ or V
CC
. Do not use ABP to provide power to exter-
nal circuitry. ABP maintains the device supply voltage
during rapid power-down conditions.
Tracking and Sequencing Modes
(
TRK
/SEQ)
To enable the power-up/power-down voltage-tracking
operation, drive TRK/SEQ low (connect TRK/SEQ to
GND). To enable power-up sequencing and power-
down tracking functions, drive TRK/SEQ high (connect
TRK/SEQ to ABP) or leave it unconnected. TRK/SEQ is
internally pulled to ABP through a 10µA current source
(see Figures 1 and 3).
Tracking
To operate in tracking mode, connect TRK/SEQ to
GND. When V
EN/UV
> 1.25V and all SET_ inputs are
above the internal SET_ threshold (0.5V), the tracking
process is initiated. The MAX6877/MAX6878/MAX6879
generate an internal reference ramp voltage that drives
the control loops for the tracked voltages. The tracking
functionality is monitored with a comparator control
block for each output (see the Functional Diagram).
The comparators monitor each OUT_ voltage with
respect to the common reference ramp voltage to
ensure the OUT_ voltages stay within 125mV of the ref-
erence ramp, monitor each tracked output voltage with
respect to its source input voltage, and monitor each
output voltage with respect to GND during power-
up/retry cycles. If for any reason any supplies fail to
track within ±250mV of the reference ramp, the FAULT
output is asserted, the power-up mode is terminated,
and all outputs are quickly powered off.
MAX6877/MAX6878/MAX6879
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
______________________________________________________________________________________ 17
During ramp up, if an OUT_ voltage is less than the ref-
erence ramp voltage by more than 125mV, the control
loop dynamically stops the control ramp voltage from
rising until the slow OUT_ voltage catches up. If an
OUT_ voltage is greater or less than the reference ramp
voltage by more than 250mV, a fault is signaled and a
power-down phase is initiated.
The slew rate for the reference ramp voltage is capaci-
tor adjustable. Connect a capacitor from SLEW to
ground to select the desired OUT_ slew rate. When all
OUT_ voltages have exceeded the V
TH_PG
percentage
of the IN_ voltage (external n-channel FET is saturated),
PG/RST asserts high after t
TIMEOUT
indicating success-
ful tracking.
Sequencing
The sequencing operation can be initiated after all
input conditions for power-up are met V
EN/UV
> 1.25V
and all SET_ inputs are above the internal SET_ thresh-
old (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turn-
ing on each channel, a delay period occurs as in
Figure 3 (programmable by connecting a capacitor
from DELAY to ground). The power-up phase for each
channel ends when its output voltage exceeds a fixed
percentage (V
TH_PG
) of the corresponding IN_ voltage.
When all channels have exceeded these thresholds,
PG/RST asserts high after t
TIMEOUT
, indicating a suc-
cessful sequence.
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneous-
ly, tracking each other. No reverse power-down
sequencing occurs.
Power-Up and Power-Down
During power-up, the OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must be
completed within the adjustable fault timeout period; oth-
erwise, the part forces a shutdown on all GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing V
EN/UV
below V
EN_F
. The
reference voltage ramp ramps down at the capacitor-
adjusted slew rate. The control-loop comparators moni-
tor each OUT_ voltage with respect to the common
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
more than V
TRK
, the control loop dynamically stops the
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
or less than the reference ramp voltage by more than
V
TRK_F
, a fault is signaled and the fast-shutdown mode
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_ and GATE _ is pulled low
with a strong I
GDS
current (see Figures 2 and 4).
Figures 5 and 6 show aborted tracking and sequencing
modes. When EN/UV goes low before t
TIMEOUT
expires, all the outputs go low and the device goes into
fast shutdown.
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pull-
down ensures that all OUT_ voltages are below V
TH_PL
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
Stability Comment
No external compensation is required for tracking or
slew-rate control.
Inputs
IN1/IN2/IN3
The highest voltage on V
CC
, IN1, IN2, or IN3 supplies
power to the device. The undervoltage threshold for
each IN_ supply is set with an external resistor-divider
from each IN_ to SET_ to ground.
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6877 features three and the MAX6878/
MAX6879 feature two externally adjustable IN_ under-
voltage lockout (UVLO) thresholds (SET1, SET2, SET3) to
enable sequencing/tracking functionality. The undervolt-
age threshold for each IN_ supply is set with an exter-
nal resistor-divider from each IN_ to SET_ to ground
(see Figure 9). All SET_ inputs must be above the inter-
nal SET_ threshold (0.5V) to enable tracking/sequenc-
ing functionality. Use the following formula to set the
UVLO threshold:
V
IN_
= V
TH
(R1 + R2) / R2
where V
IN_
is the undervoltage lockout threshold and
V
TH
is the 500mV SET threshold.
Margin Input (
MMAARRGGIINN
)
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
MAX6877/MAX6878/MAX6879
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
18 ______________________________________________________________________________________
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/RST and FAULT outputs
does not change while MARGIN is low. PG/RST,
FAULT, and all monitoring functions are disabled while
MARGIN is low. MARGIN makes it possible to vary the
supplies without a need to adjust the thresholds to pre-
vent tracker/sequencer alerts or faults. Drive MARGIN
high or leave it unconnected for normal operating
mode.
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
(C
SLEW
) from SLEW to ground. Use the following for-
mula to calculate the typical slew rate:
Slew Rate = (9.35 x 10
-8
)/ C
SLEW
where slew rate is in V/s and C
SLEW
is in farads.
The capacitor at C
SLEW
also sets the FAULT timeout
period (t
FAULT
) and FAULT retry timeout period
(t
RETRY
) (see Table 1).
For example, if C
SLEW
= 100pF, we have t
RETRY
=
350ms, t
FAULT
= 21.91ms, slew rate = 935V/s. For
example, if C
SLEW
= 1nF, we have t
RETRY
= 3.5s,
t
FAULT
= 219ms, slew rate = 93.5V/s.
C
SLEW
is the capacitor on the SLEW pad, and must be
large enough to make the parasitic capacitance negli-
gible. C
SLEW
should be in the range of 100pF <
C
SLEW
< 1nF.
Limiting Inrush Current
The capacitor connected at SLEW controls the OUT_S
slew rate, thus controlling the inrush current required to
charge the load capacitor at the outputs (OUT_). Using
the programmed slew rate, limit the inrush current by
using the following formula:
I
INRUSH
= C
OUT
x SR
where I
INRUSH
is in amperes, C
OUT
is in farads, and SR
is in V/s.
Delay Time Input (DELAY)
To adjust the desired delay period (t
DELAY
) before
tracking/sequencing is enabled, connect a capacitor
(C
DELAY
) between DELAY to ground (see Figures 1 to 8).
The selected delay time is also enforced when EN/UV
rises from low to high when all the input voltages
(IN1/IN2/IN3) are present. Use the following formula to
calculate the delay time:
t
DELAY
= 200µs + (500kΩ x C
DELAY
)
where t
DELAY
is in µs and C
DELAY
is in farads. Leave
DELAY unconnected for the default 200µs delay.
Timeout Period Input (TIMEOUT)
These devices feature a PG/RST timeout period.
Connect a capacitor (C
TIMEOUT
) from TIMEOUT to
ground to program the PG/RST timeout period. After all
OUT_ outputs exceed their IN_ referenced thresholds
(V
TH_PG
), PG/RST remains low for the selected timeout
period, t
TIMEOUT
(see Figure 3):
t
TIMEOUT
= 200µs + (500kΩ x C
TIMEOUT
)
where t
TIMEOUT
is in µs and C
TIMEOUT
is in farads.
Leave TIMEOUT unconnected for the default 200µs
timeout delay.
Logic-Enable Input (EN/
UV
)
Drive logic EN/UV input above V
EN_R
to initiate voltage
tracking/sequencing during the power-up operation.
Drive logic EN/UV below V
EN_F
to initiate tracking
power-down operation. Connect EN/UV to an external
resistor-divider network to set the external undervoltage
lockout threshold.
OUT1/OUT2/OUT3
The MAX6877 monitors three and MAX6878/MAX6879
monitor two OUT_ outputs to control the tracking/
sequencing performance. After the internal supply
(ABP) exceeds the minimum voltage (2.7V) require-
ments, EN/UV > V
EN_R
, and IN1/IN2/IN3 are all greater
than their adjusted SET_ thresholds, OUT1/OUT2/OUT3
begin to track or sequence.
Table 1. C
SLEW
Timing Formulas
TIME PERIOD FORMULAS
Slew Rate (9.35 x 10
-8
) / C
SLEW
t
RETRY
3.506 x 10
9
x C
SLEW
t
FAULT
2.191 x 10
8
x C
SLEW
IN_
R1
R2
V
IN_
SET_
MAX6877
MAX6878
MAX6879
Figure 9. Setting the Undervoltage (UVLO) Thresholds
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

MAX6879ETE+T

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Buy MAX6879ETE+T
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Dual Power-Sup Sequencer
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