7
Table 6. Switching Specications
Over recommended operating conditions T
A
= -40 °C to 100 °C, V
CC
= +4.5 V to 20 V, I
F(ON)
= 6 mA to 10 mA, V
F(OFF)
= 0
V to 0.8 V, unless otherwise specied. All typicals at T
A
= 25 °C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time to
Logic Low Output Level
t
PHL
150 350 ns With Peaking
Capacitor
5, 6 1
Propagation Delay Time to
Logic High Output Level
t
PLH
110 350 ns With Peaking
Capacitor
5, 6 1
Pulse Width Distortion |t
PHL
- t
PLH
|
= PWD
250 ns 2
Propagation Delay Dierence
Between Any 2 Parts
PDD -100 250 ns 3
Output Rise Time (10-90%) t
r
16 ns 5, 8
Output Fall Time (90-10%) t
f
20 ns 5, 8
Logic High Common Mode
Transient Immunity
|CM
H
| 20 kV/µs |V
CM
| = 1000 V, I
F
= 6.0
mA, V
CC
= 5 V, T
A
= 25˚C
11 4
Logic Low Common Mode
Transient Immunity
|CM
L
| 20 kV/µs |V
CM
| = 1000 V, V
F
= 0 V,
V
CC
= 5 V, T
A
= 25˚C
11 4
Table 7. Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary
Withstand Voltage*
V
ISO
3750** V
rms
RH < 50%, t = 1 min.
T
A
= 25°C
5, 6
5000***
Input-Output Resistance R
I-O
10
12
V
I-O
= 500 Vdc 5
Input-Output Capacitance C
I-O
0.6 f = 1 MHz, V
I-O
= 0 Vdc 5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable).
** For all ACPL-P480 devices except Option 020
*** For ACPL-W480 and Option 020 of ACPL-P480)
Notes:
1. The t
PLH
propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The t
PHL
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse.
2. Pulse Width Distortion (PWD) is dened as |t
PHL
- t
PLH
| for any given device.
3. The dierence between t
PLH
and t
PHL
between any two devices under the same test condition.
4. CM
H
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, V
O
> 2.0 V.
CM
L
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, V
O
< 0.8 V.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V
RMS
for one second (leakage
detection current limit, I
I-O
≤ 5 µA). ; each optocoupler with option 020 is proof tested by applying an insulation test voltage ≥ 6000 V
RMS
for
1 second (leakage detection current limit, I
I-O
≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b)
shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
7. Use of a 0.1 μF bypass capacitor connected between pins 4 and 6 is recommended.
