MC74LVX4245
www.onsemi.com
6
Dual Supply Octal Translating Transceiver
The 74LVX4245 is a is a dual−supply device well capable
of bidirectional signal voltage translation. This level shifting
ability provides an excellent interface between low voltage
CPU local bus and a standard 5.0 V I/O bus. The device
control inputs can be controlled by either the low voltage
CPU and core logic or a bus arbitrator with 5.0 V I/O levels.
The LVX4245 is ideal for mixed voltage applications such
as notebook computers using a 3.3 V CPU and 5.0 V
peripheral devices.
Applications:
Mixed Mode Dual Supply Interface Solutions
The LVX4245 is designed to solve 3.0 V / 5.0 V interfaces
when CMOS devices cannot tolerate I/O levels above their
applied V
CC
. If an I/O pin of a 3.0 V device is driven by a 5.0
V device, the P−Channel transistor in the 3.0 V device will
conduct − causing current flow from the I/O bus to the 3.0 V
power supply. The result may be destruction of the 3.0 V
device through latchup effects. A current limiting resistor
may be used to prevent destruction, but it causes speed
degradation and needless power dissipation.
A better solution is provided in the LVX4245. It provides
two different output levels that easily handle the dual voltage
interface. The A port is a dedicated 5.0 V port; the B port is
a dedicated 3.0 V port.
Since the LVX4245 is a ‘245 transceiver, the user may
either use it for bidirectional or unidirectional applications.
The center 20 pins are configured to match a ‘245 pinout.
This enables the user to easily replace this level shifter with
a 3.0 V ‘245 device without additional layout work or re−
manufacture of the circuit board (when both buses are 3.0 V).
Figure 3. 3.3V/5V Interface Block Diagram
LVX4245
V
CCB
V
CCA
LVX4245
V
CCB
V
CCA
EISA - ISA - MCA
(5V I/O LEVELS)
LOW VOLTAGE CPU LOCAL BUS
Powering Up the LVX4245
When powering up the LVX4245, please note that if the
V
CCB
pin is powered−up well in advance of the V
CCA
pin,
several milliamps of either I
CCA
or I
CCB
current will result.
If the V
CCA
pin is powered−up in advance of the V
CCB
pin
then only nanoamps of Icc current will result. In actuality the
V
CCB
can be powered “slightly” before the V
CCA
without
the current penalty, but this “setup time” is dependent on the
power−up ramp rate of the V
CC
pins. With a ramp rate of
approximately 50 mV/ns (50V/ms) a 25 ns setup time was
observed (V
CCB
before V
CCA
). With a 7.0 V/ms rate, the
setup time was about 140ns. When all is said and done, the
safest powerup strategy is to simply power V
CCA
before
V
CCB
. One more note: if the V
CCB
ramp rate is faster than
the V
CCA
ramp rate then power problems might still occur,
even if the V
CCA
powerup began prior to the V
CCB
powerup.
